Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2011-05-03
2011-05-03
Baderman, Scott T (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S001000, C714S047300
Reexamination Certificate
active
07937615
ABSTRACT:
In a system including a plurality of multi-core processors, a table for managing the processors and cores owned by the processors is provided and a single virtual server is formed by using cores owned by different processors when generating the virtual server. According to the number owned by processors, the number of processors is varied. If a fault preecho in a processor is detected, control is exercised so as not to deliver an execution schedule of a virtualization mechanism to the processor in which the fault preecho has been detected. In a system including a plurality of multi-core processors, arithmetic cores owned by a plurality of different processors are assigned to processing of a process or thread in an operating system. In a system including a plurality of multi-core processors, arithmetic cores owned by a plurality of different processors are assigned to the operating system.
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Japanese Office Action, w/ partial English translation thereof, issued in Japanese Patent Application No. JP 2006-340673 dated Apr. 8, 2009.
Horie Toru
Takamoto Yoshifumi
Baderman Scott T
Butler Sarai
Hitachi , Ltd.
McDermott Will & Emery LLP
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