Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2005-11-01
2005-11-01
Dang, Khanh (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S310000
Reexamination Certificate
active
06961800
ABSTRACT:
Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.
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Blocker Jim
Chin Kenneth T.
Jones Phillip M.
Larson John E.
Lester Robert A.
Dang Khanh
Hewlett--Packard Development Company, L.P.
Vu Trisha
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