Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2005-06-14
2005-06-14
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S626000, C438S691000, C438S692000, C438S129000, C438S424000, C438S631000, C438S645000, C438S599000, C257S752000, C257S750000, C257S620000
Reexamination Certificate
active
06905967
ABSTRACT:
In a feature layer of a semiconductor wafer, dummy tiles which overcome the tendency of dishing and erosion to occur during a CMP process are placed with various sizes and in various positions. An isolation zone is provided around active features. A scanning process of the feature layout surveys oxide density and nitride density over the wafer layer outside of said isolation zone. Values of the ratios of oxide
itride density for two or more length scales which define tiling zones, are calculated. Tile placement and sizing in the zones is dependent upon the oxide
itride density ratio values; and further upon an oxide deposition model specific to the oxide used in the fabrication process and upon a polishing model of the CMP process being employed.
REFERENCES:
patent: 5278105 (1994-01-01), Eden et al.
patent: 5854125 (1998-12-01), Harvey
patent: 5885856 (1999-03-01), Gilbert et al.
patent: 6323113 (2001-11-01), Gabriel et al.
patent: 6358816 (2002-03-01), Singh et al.
patent: 6396158 (2002-05-01), Travis et al.
patent: 6593226 (2003-07-01), Travis et al.
patent: 6611045 (2003-08-01), Travis et al.
patent: 6770929 (2004-08-01), Singh et al.
Kahng et al., Filling Algorithms and Analysis for Layout Density Control., IEEE Transaction On Computer Aided Design Of Integrated Circuits and Systems., vol. 18, No. 4, Apr. 1999.
Stine et al., The Physical and Electrical Effects of Metal-Fill Patterning Practices for Oxide Chemical-Mechanical Polishing Process., IEEE Transaction On Electron Devices,, vol. 45., No. 3, Mar. 1998.
Brown Thomas Michael
Tian Ruiqi
Travis, Jr. Edward Outlaw
AMD Inc.
Graves Charles E.
Keshavan Belur
Motorola Inc.
Smith Matthew
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