Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-24
2003-07-29
Niebling, John E (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S624000
Reexamination Certificate
active
06599823
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating multi-level interconnection lines, and relates more particularly to a method for improving bond structure formed of multi-level interconnection lines and low K inter-metal dielectric, especially fabricated by a dual damascene process.
2. Description of the Prior Art
Many highly integrated semiconductor circuits utilize multi-level wiring line structures for interconnecting regions within devices and for interconnecting one or more devices within the integrated circuit. In forming such structures, it is conventional to provide first or lower level wiring lines or interconnect structures and then to form a second level wiring lines in contact with the first level wiring lines or interconnect structures. A first level interconnect might be formed in contact with a doped region within the substrate of an integrated circuit device. Alternatively, a first level interconnect might be formed to a polysilicon or metal wiring lines that is in contact with one or more device structure in or on the substrate of the integrated circuit device. One or more interconnections are typically formed between the first level wiring lines or interconnect and other portions of the integrated circuit device or to structures external to the integrated circuit. This is accomplished, in part, through the second level of wiring lines.
A dual damascene process is intensively developed to provide a more stable and more advanced method of fabricating interconnects in an integrated circuit. By using a chemical mechanical polishing process during the dual damascene process, a greater variety of metals such as aluminum, copper and aluminum alloy can be selected without being restricted by the conventional etching process. Selecting from a greater variety of metals is advantageous to the requirement of low resistance interconnects, and is also advantageous in preventing electromigration.
However, as the dimension of devices on a chip becomes smaller and smaller, the density of interconnect pitch is higher and higher. For a common dielectric layer, for example, a silicon dioxide layer, due to the high dielectric constant, a higher RC delay is easily caused. Therefore, this kind of dielectric layer is not used as an inter-metal dielectric (IMD) in an integrated circuit with high density. To apply a low K dielectric layer has an advantage such as reducing the interconnection parasitic capacitance, consequently reducing the RC delay, or mitigating the cross talk between the metal lines, hence, the operation is improved.
While, as shown in
FIG. 1
, a bond structure fabricated by a dual damascene process, which consists of a plurality of alternative multi-level copper interconnection lines and via layers filled with copper and a low K dielectric filled therein as the inter-metal dielectric, encounters the issue of bondability between the copper interconnection line and the low K dielectric. The low K dielectric, such as low K spin-on glass (SOG), is intrinsically too soft to resist the force of the package bonding of the bond structure, and the poor adhesion between copper and the low K SOG actually does not endure the pulling force from the package equipment during proceeding package bonding.
Accordingly, it is desirable to develop a method for improving package bonding of the multi-level interconnection lines and the low K inter-metal dielectric.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide a method for improving package bonding between multi-level interconnection lines and low K inter-metal dielectric, in which a trench is formed between each pair of the interconnection lines on one level of the multi-level interconnection lines, and then filling the trench with an oxide dielectric instead of the low K inter-metal dielectric filled therein before. The oxide dielectric is hard enough to resist the force of the package bonding, and hence the relibility of bondability for the interconnection line and the low K inter-metal dielectric is improved.
It is another object of the present invention to provide a method for improving package bonding between multi-level interconnection lines and low K inter-metal dielectric, in which an oxide dielectric is used instead of one portion of the low K inter-metal dielectric filled in the multi-level interconnection lines structure. Thereby, the oxide dielectric can enhance adhesion between the interconnection lines and the low K inter-metal dielectric, and endure the pulling force from the package equipment during proceeding package bonding.
It is a further object of the present invention to provide a method for improving package bonding between multi-level interconnection lines and low K inter-metal dielectric. The present method is simple and readily attained, and does not increase complexity of the original process.
In order to achieve the above objects, the present invention provides a method for improving package bonding between multi-level interconnection lines and low K inter-metal dielectric. Firstly, providing a semiconductor substrate with a layered structure having a top interconnection line layer, a bottom interconnection line layer and a plurality of alternative interconnection line layers and via layers formed therebetween, each of the vias being in alignment with one adjacent upper interconnection line and one adjacent lower interconnection line, wherein a low K dielectric material is filled in the layered structure as the inter-metal dielectric. Then, patterning the layered structure to form a trench between each pair of the adjacent interconnection lines on one layer of the layered structure. Subsequently, forming a first oxide layer over the layered structure to fill the trench formed therein and then planarizing the first oxide layer. Thereafter, forming a second oxide layer over the first oxide layer, and patterning the second oxide layer to form a plurality of openings each of which being in alignment with each of the top interconnection lines. Finally, forming a conductive layer over the second oxide layer to fill the openings to form a plurality of plugs, and then patterning the conductive layer to form a conductive pad across over each pair of the plugs formed within the second oxide layer. The first oxide dielectric is used instead of one portion of the low K dielectric in the multi-level interconnection lines structure. The first oxide dielectric is hard enough to resist the force of the package bonding between the multi-level interconnection lines and the low K dielectric, and thereby the reliability of bondability of the bond structure formed of the multi-level interconnection lines and the low K inter-metal dielectric is enhanced.
REFERENCES:
patent: 6016000 (2000-01-01), Moslehi
patent: 6180976 (2001-01-01), Roy
Isaac Stanetta
Niebling John E
United Microelectronics Corp.
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