Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-06-28
2003-05-27
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C216S088000, C438S754000
Reexamination Certificate
active
06569770
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of preventing oxide erosion in a tungsten plug process in the manufacture of integrated circuits.
(2) Description of the Prior Art
In a typical tungsten plug process, openings are etched in a dielectric layer to contact underlying semiconductor device regions. A metal layer, such as tungsten or aluminum, is deposited over the dielectric layer and within the openings. The excess metal over the dielectric layer may be polished away using chemical mechanical polishing (CMP). Usually, the dielectric layer is an oxide layer.
FIG. 1A
illustrates tungsten filled openings through an oxide layer
18
overlying a semiconductor substrate
10
. In section A, an isolated tungsten plug is shown. Section B shows a dense plug area. Tungsten
30
and barrier metal layer
28
are to be polished away over the oxide layer to leave tungsten plugs only within the openings.
FIG. 1B
illustrates the device after chemical mechanical polishing (CMP). Plug dishing C occurs in the isolated plug area A. Both plug dishing and oxide erosion D occur in the dense plug area B. Oxide erosion control is a challenge unique to the tungsten chemical mechanical polishing planarization process because 1) high oxide erosion brings about difficulties in subsequent lithography and etch steps and 2) high oxide erosion is a major cause of contact/via seam exposure as device sizes shrink to sub-quarter-micron technology. This exposure degrades electrical performance. Currently, major efforts on oxide erosion have focused on slurry composition, pad hardness, and process parameter optimization (e.g. platen speed and carrier down-force, etc.). Only limited improvement is gained from these methods.
U.S. Pat. No. 6,001,730 to Farkas et al teaches a two-step CMP of copper where a tantalum nitride barrier layer also acts as a polish stop. This barrier layer must be removed to avoid short circuiting. Removal of the barrier layer will cause oxide erosion. U.S. Pat. No. 6,057,602 to Hudson et al uses a low friction material such as graphitic carbon in polishing tungsten to reduce oxide loss at the field oxide area. There is no evidence that this graphitic carbon can help to reduce oxide erosion in the dense metal plug area. U.S. Pat. No. 6,071,809 to Zhao shows a double polish stop of silicon dioxide over silicon nitride in polishing metal including tungsten and copper. U.S. Pat. No. 6,048,796 to Wang et al teaches a silicon nitride protective layer over oxide. After CMP of a copper and barrier metal layer, the protective layer prevents penetration of the oxide layer by conductive particles left after CMP. U.S. Pat. No. 5,385,867 to Ueda et al discloses the use of a barrier layer as polish stop in the CMP of Al—Cu—Si. Removal of the conductive barrier layer causes oxide erosion. Co-pending U.S. patent application Ser. No. 09/442,493 to S. Gupta et al filed on Nov. 19, 1999 teaches using a silicon nitride diffusion step layer in a copper plug process. In the case of direct copper etch, the silicon nitride is an etch stop layer. In the case of dual damascene, silicon nitride is deposited on the oxide surface with the copper trench exposed after copper CMP. The silicon nitride layer is used to prevent copper from diffusing into the oxide. Allowed U.S. patent application Ser. No. 09/110,419 to R. R. Sudipto filed on Jul. 6, 1998 teaches the use of a titanium nitride polish stop layer in a tungsten plug process. Again, when the titanium nitride layer is removed, oxide erosion will occur.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of metal plug formation in the fabrication of integrated circuit devices.
Another object of the invention is to provide a method of reducing oxide erosion in the metal plug process.
Yet another object of the invention is to reduce oxide erosion in the metal plug process by employing a silicon nitride polish stop layer over the oxide.
A further object of the invention is to reduce oxide erosion in the tungsten or aluminum plug process by employing a silicon nitride polish stop layer over the oxide.
In accordance with the objects of this invention a new method to prevent oxide erosion in a metal plug process by employing a silicon nitride layer over the oxide is achieved. An oxide layer is deposited overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the oxide layer. Openings are etched through the silicon nitride layer and into the oxide layer. A barrier metal layer is deposited overlying the silicon nitride layer and into the openings. A metal layer is deposited overlying the barrier metal layer. The metal layer and barrier metal layer are polished away using chemical mechanical polishing (CMP) with a polish stop at the silicon nitride layer. The metal layer forms metal contacts and via plugs. The silicon nitride layer prevents erosion of the oxide layer during the polishing step to complete formation of metal contacts and via plugs in the fabrication of an integrated circuit device.
REFERENCES:
patent: 5385867 (1995-01-01), Ueda et al.
patent: 6001730 (1999-12-01), Farkas et al.
patent: 6048796 (2000-04-01), Wang et al.
patent: 6057602 (2000-05-01), Hudson et al.
patent: 6071809 (2000-06-01), Zhao
patent: 6207570 (2001-03-01), Mucha
patent: 6274499 (2001-08-01), Gupta et al.
Co-pending U.S. patent application Ser. No. 09/442,493 to S. Gupta et al. filed on Nov. 19, 1999.
Allowed U.S. patent application Ser. No. 09/110,419 to R.R. Sudipto filed on Jul. 6, 1998.
Balakumar Subramanian
Wang Cuiyang
Wang Xian Bin
Xu Yi
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L.S.
Powell William A.
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