Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-10-28
2008-10-07
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07434197
ABSTRACT:
A hot spot is identified within a mask layout design. The hot spot represents a local region of the mask layout design having one or more feature geometries susceptible to producing one or more fabrication deficiencies. A test structure is generated for the identified hot spot. The test structure is defined to emulate the one or more feature geometries susceptible to producing the one or more fabrication deficiencies. The test structure is fabricated on a test wafer using specified fabrication processes. The as-fabricated test structure is examined to identify one or more adjustments to either the feature geometries of the hot spot of the mask layout design or the specified fabrication processes, wherein the identified adjustments are capable of reducing the fabrication deficiencies.
REFERENCES:
patent: 6782525 (2004-08-01), Garza et al.
patent: 6954911 (2005-10-01), Pierrat
patent: 6968527 (2005-11-01), Pierrat
patent: 2004/0019870 (2004-01-01), Ohmori
Burrows Jonathan O.
Ciplickas Dennis
Davis Joseph C.
Dolainsky Christoph
Hess Christopher
Chiang Jack
PDF Solutions, Inc.
Tat Binh C
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