Method for improving manufacturing process of self-aligned conta

Details Method for improving manufacturing process of self-aligned conta Method for improving manufacturing process of self-aligned conta

1999-10-26

2000-12-26

Smith, Matthew

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438585, 438584, 257202, 257303, H01L 213205

Patent

active

061658790

ABSTRACT:
The invention is related to a method for increasing margin precision of a self-aligned contact. A semiconductor has at least a gate electrode and source/drain, and a gate spacer is formed on the sidewall of the gate electrode. A first silicon oxide layer is then formed on the semiconductor substrate. A hard mask layer is formed on the first silicon oxide layer. A second silicon oxide layer is then deposited over the hard mask layer. A chemical mechanical polishing is then performed to remove the second silicon oxide layer so that the hard mask layer is planarized. Thereafter, the hard mask layer and the first silicon oxide layer is etched to form a gap region on the first silicon oxide layer. A polysilicon layer is then deposited over the entire substrate including the gap region and the hard mask layer. Thereafter, the polysilicon layer is etched back to form a polysilicon spacer. Finally, the gap region of the first silicon oxide layer is etched to form a self-aligned contact.

REFERENCES:
patent: 5019525 (1990-07-01), Virkus et al.
patent: 5104822 (1992-04-01), Butler
patent: 5612240 (1996-06-01), Chang
patent: 5888897 (1999-03-01), Liang
patent: 6015730 (1998-03-01), Wang et al.

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