Electrical computers and digital data processing systems: input/ – Interrupt processing – Handling vector
Reexamination Certificate
1999-12-17
2001-03-20
Ray, Gopal C. (Department: 2781)
Electrical computers and digital data processing systems: input/
Interrupt processing
Handling vector
C710S260000, C713S400000
Reexamination Certificate
active
06205509
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
BACKGROUND OF THE INVENTION
The present invention relates to interrupt processing techniques employed within a computer system and more specifically, to a method and apparatus for rapidly identifying the source of an interrupt. In digital systems employing processors, normal program execution is halted to respond to the detection of either an asynchronous or a synchronous event, which may be associated with a peripheral device. Upon the occurrence of such an event, an interrupt signal is generated to provide an indication to the processor that the peripheral device requires service. Typically, the interrupt signals of various peripheral devices are wire OR'd together since the number of interrupt events that may need to be accommodated can exceed the number of interrupt signals that are supported by present processors. Often there are several interrupt signals going directly to the processor, however, even where multiple interrupt signals are employed the interrupt cannot be classified based solely upon the interrupt signal alone. The processor, upon detection of an interrupt via the assertion of an interrupt signal, vectors to an interrupt handler, and, using standard bus accesses, determines the source of the interrupt by testing interrupt bits associated with devices capable of triggering the relevant interrupt signal. After, or during servicing of the interrupt, the processor uses standard bus accesses to clear the source of the interrupt and thereby re-arm the system.
In conventional processing systems, the execution of the above described tasks wastes considerable time in determining the source of the interrupt and later, in clearing the interrupt, due to the number of bus accesses that are required during the interrupt handling process. The overhead is the result of the intrinsic latency of the bus as well as delays incurred in reading and writing buffers, which are electrically situated between the processor and the bus.
It would therefore be desirable to have a technique for determining the source of an interrupt, which avoids the latency, associated with traditional interrupt detection mechanisms.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a method and apparatus are disclosed for rapidly identifying the source of an interrupt. An interrupt state register containing plural bits receives signals indicative of interrupt events and individual bits of the interrupt state register are set in response to such event signals. Output signals corresponding to individual bits of the interrupt state register are coupled to bits of an interrupt vector register which are synchronized with the clock of a processor. The interrupt vector register is a memory-mapped read/write register, which can be directly read by the processor. Individual bits of the interrupt vector register provide an indication of the occurrence of a given interrupt. The processor may identify the source of the interrupt by reading the interrupt vector register. Plural clear signals are provided which may be asserted under the control of the processor and which, in a preferred embodiment, correspond in number to the number of bits in the interrupt state register. The processor clears selected bits of the interrupt state register by writing to an interrupt clear register. A write to the interrupt clear register by the processor generates a single cycle clock pulse for each asserted data bit in the clear register. The clear pulses are transmitted over a bus and serve to clear the respective bits of the interrupt state register.
To identify the source of the interrupt, bit test instructions are employed after the interrupt vector register is read by the processor and the contents of the interrupt vector register are loaded into a general purpose processor register. Bus cycles associated with the identification of the interrupt source are avoided. Since the interrupt vector register is memory-mapped like data/instruction memory, the processor can issue a read instruction to access the contents of the interrupt vector register. The interrupt state register may also be accessed over a bus, which couples the interrupt state register to the processor.
In addition of the above-referenced state register, a second state register may optionally be provided which is only accessible over the bus. Thus first and second registers are provided for storing interrupt events and a mechanism is provided to permit more rapid access to the contents of the first interrupt state register than the second interrupt state register.
The disclosed technique is particularly advantageous in embedded processor Application Specific Integrated Circuit (ASIC) designs in which the signaling overhead associated with the presently disclosed mechanism does not impose a significant cost or space burden.
REFERENCES:
patent: 4428044 (1984-01-01), Liron
patent: 4845752 (1989-07-01), Blanc et al.
patent: 4994960 (1991-02-01), Tuchler et al.
patent: 5410710 (1995-04-01), Sarangdhar et al.
patent: 5892956 (1999-04-01), Qureshi et al.
Chieffo Paul
Platko John J.
3Com Corporation
Ray Gopal C.
Weingarten, Schurgin Gagnebin & Hayes LLP
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