Method for improving efficiency in laying out electronic...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000

Reexamination Certificate

active

11088321

ABSTRACT:
A method is proposed for improving the layout efficiency in laying out electronic components, which is applicable to information processing equipment, to accelerate the layout of electronic components. First, a first two-dimensional plan view including various electronic component members is preset using a drafting software platform. Subsequently, the two-dimensional plan view is converted to a text file and all the relevant data of the electronic components contained in the two-dimensional plan view are encoded in the text file. Then, all of the electronic component members contained in the first two-dimensional plan view are displayed in a second two-dimensional plan view, and a function selection menu is generated by an arithmetic process. Therewith, a user is able to select the data of the electronic component contained in the text file via the function selection menu to perform the layout operations for a printed circuit board.

REFERENCES:
patent: 5187784 (1993-02-01), Rowson
patent: 5901066 (1999-05-01), Hong
patent: 2002/0018583 (2002-02-01), Gont et al.
patent: 2004/0143803 (2004-07-01), Cowan et al.
patent: 2006/0098026 (2006-05-01), Benayoun et al.
patent: 2006/0156268 (2006-07-01), Wen et al.

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