Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-09-02
2001-09-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S528000, C438S689000
Reexamination Certificate
active
06284660
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the fabrication of integrated circuits, and more particularly to structures and methods for improving the polishing steps in the fabrication of integrated circuits.
DISCUSSION OF RELATED ART
Integrated circuits are produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer which is subsequently divided into identical dies or chips. It is often desirable to provide a planar topography before a subsequent layer is formed. A nonplanar topography creates problems in the patterning of subsequent layers. Such problems include, for example, limited depth of focus by the photolithographic system, metal residues during reactive ion etching, and poor metal step coverage.
A process commonly used in fabrication of integrated circuits to create a planar topography is chemical mechanical polishing (CMP). This process involves chemically etching of a surface while also mechanically grinding or polishing it. The combined action of surface chemical reaction and mechanical polishing allows for a controlled, layer by layer removal of a desired material from the wafer surface, resulting in a preferential removal of protruding surface topography and a planarized wafer surface.
Chemical mechanical polishing (CMP), also referred to in the art as chemical mechanical planarization (CMP), involves holding or rotating a wafer of semiconductor material against a wetted polishing surface under controlled chemical slurry, pressure, and temperature conditions. A chemical slurry containing a polishing agent such as alumina or silica may be utilized as the abrasive medium. Additionally, the chemical slurry may contain chemical etchants. This procedure may be used to produce a surface with a desired endpoint or thickness, which also has a polished and planarized surface. Such apparatus for polishing semiconductor wafers are disclosed in U.S. Pat. Nos. 4,193,226 and 4,811,522. Another such apparatus is manufactured by Westech Engineering and is designated as a Model 372 Polisher.
In a typical CMP process, a wafer is pressed against a polishing pad in the presence of a slurry under controlled chemical, pressure, velocity, and temperature conditions. The slurry solution generally contains small, abrasive particles that abrade the surface of the wafer, and chemicals that etch and/or oxidize the surface of the wafer. The polishing pad is generally a planar pad made from a continuous phase matrix material such as polyurethane. Thus, when the pad and/or the wafer moves with respect to the other, material is removed from the surface of the wafer by the abrasive particles (mechanical removal) and by the chemicals (chemical removal) in the slurry.
FIG. 1
schematically illustrates a conventional CMP machine
10
with a platen
20
, a wafer carrier
30
, a polishing pad
40
, and a slurry
44
on the polishing pad. An under-pad
25
is typically attached to the upper surface
22
of the platen
20
, and the polishing pad
40
is positioned on the under-pad
25
. In the conventional CMP machines, a drive assembly
26
rotates the platen
20
in a direction indicated by arrow A. However, alternatively the drive assembly
26
may also reciprocate the platen
20
back and forth in the direction indicated by arrow B. The motion of the platen
20
is imparted to the pad
40
through the under-pad
25
because the polishing pad
40
frictionally engages the under-pad
25
. The wafer carrier
30
has a lower surface
32
to which a wafer
12
may be attached, or the wafer
12
may be attached to a resilient pad
34
positioned between the wafer
12
and the lower surface
32
. The wafer carrier
30
may be a weighted, free floating wafer carrier, but an actuator assembly
36
is preferably attached to the wafer carrier
30
to impart axial and rotational motion, as indicated by arrows C and D, respectively.
In the operation of the conventional CMP machine
10
, the wafer
12
faces downward against the polishing pad
40
, and then the platen
20
and the wafer carrier
30
move relative to one another. As the face of the wafer
12
moves across the planarizing surface
42
of the polishing pad
40
, the polishing pad
40
and the slurry
44
remove material from the wafer
12
. CMP processes typically remove either conductive materials or insulative materials from the surface of the wafer to produce a flat, uniform surface upon which additional layers of devices may be fabricated.
However, conventional CMP creates micro scratches on the surface of the layer being polished. These micro scratches are particularly problematic in interconnection schemes. For example, the scratches formed during CMP are filled with metal as the metal layer is deposited. As dimensions of feature size becomes increasingly smaller, there is a greater probability that a scratch contacting adjacent metal lines may exist. The metal trapped in such a scratch creates a short between the adjacent metal lines with which it is in contact, thus rendering the device defective.
Therefore, there exist a need to provide a CMP method that reduces defects causes by scratching and increases the speed of the CMP process.
SUMMARY OF THE INVENTION
The present invention provides a method of fabrication of an integrated circuit, the method including altering a portion of a surface layer of a material to be polished and polishing the surface layer in a chemical mechanical polishing process. Preferably, the step of altering of the present invention includes adding an impurity to the material such as a dopant to the material layer.
The above and other advantages and features of the invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings.
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Dickstein , Shapiro, Morin & Oshinsky, LLP
Lytle Craig P.
Micro)n Technology, Inc.
Smith Matthew
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