Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-04-14
2008-03-25
Whitmore, Stacy (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07350179
ABSTRACT:
A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of said representation of said relation. A synthesized gate for said gate representing said OR function and synthesis of a set of representations of relations by iterating said building step and said creating step over one or more variables in said representation of said relation is performed to accumulate a synthesized gate set, which synthesized gate set is returned.
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Kukula et al., Computer Aided Verification, 12thInternational Conference on Computer Aided Verification, Jul. 15-19, 2000.
Moon et al., Simplifying Circuits for Formal Verification Using Parametric Representation, Formal Methods in Computer-Aided Design, 2002, pp. 52-69.
Yuan et al., Constraint Synthesis for Environment Modeling in Functional Verification, Design Automation Conference, Jun. 2-6, 2003.
Baumgartner Jason Raymond
Janssen Geert
Mony Hari
Paruthi Viresh
Dillon & Yudell LLP
International Business Machines - Corporation
Salys Casimer K.
Whitmore Stacy
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