Multiplex communications – Wide area network – Packet switching
Patent
1995-03-07
1996-09-10
Hsu, Alpus H.
Multiplex communications
Wide area network
Packet switching
370 68, H04Q 1104
Patent
active
055552455
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to a method for implementing time switching, and to a time switch.
In this connection, time switch refers to a device capable of switching the contents of any time slot in the frame structure of an incoming signal to any time slot in an outgoing frame structure. In addition to a time switch, this device can also be called a time slot interchanger.
Cross-connection of a TDM (Time Division Multiplex) signal is effected in a time switch comprising a connection memory into which the contents of incoming time slots are written, and on the one hand, means for controlling writing into the memory, and on the other other hand, means for controlling reading from the memory. Switching data is stored in an address control memory of the time switch, the memory locations of which are read cyclically--one memory location per each outgoing time slot. The contents of a memory location indicate that memory location of the connection memory from which the information is read.
In known solutions, switching data consists of the absolute address of a time slot, i.e. that time slot of an outgoing signal which is outgoing at that particular moment is given the number of the incoming time slot the contents of which are to be switched to the outgoing time slot.
The known solutions have the drawback of making the equipment fairly complicated.
SUMMARY OF THE INVENTION
The object of the present invention is to remedy the above-mentioned drawback.
The idea of the invention is to indicate the read address necessary for reading from the memory as a relative transition occurring within the frame structure.
The solution of the invention renders it possible to implement a time switch in a more simplified manner than before. As a result of the simplification of hardware, the delay caused by it is shorter, which leads to improved reliability of operation.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following, the invention will be described in more detail with reference to the examples based on the STM-1 signal and set forth in the accompanying drawings, in which
FIG. 1 shows the basic structure of a single STM-N frame,
FIG. 2 shows the structure of a single STM-1 frame,
FIG. 3 shows the assembly of the STM-N frame from existing PCM systems,
FIG. 4 shows an STM-1 frame and blocks of different sizes contained in it,
FIG. 5 shows a time switch of the invention and implementation of time switching,
FIG. 6 shows a more detailed view of the read unit of the time switch shown in FIG. 6.
DETAILED DESCRIPTION
FIG. 1 illustrates the structure of an STM-N frame used in the Sychronous Digital Hierarchy (SDH) network, and FIG. 2 illustrates a single STM-1 frame. The STM-N frame comprises a matrix with 9 rows and N.times.270 columns so that there is one byte at the junction point between each row and the column. Rows 1-3 and rows 5-9 of the N.times.9 first columns comprise a section overhead SOH, and row 4 comprises an AU pointer. The rest of the frame structure is formed of a section having the length of N.times.261 columns and containing the payload section of the STM-N frame.
FIG. 2 illustrates a single STM-1 frame which is 270 bytes in length, as described above. The payload section comprises one or more administration units AU. In the example shown in the figure, the payload section consists of the administration unit AU-4, into which a highest-level virtual container VC-4 is inserted. (Alternatively, the STM-1 transfer frame may contain three AU-3 units, each containing a corresponding lower-level virtual container VC-3). The VC-4 in turn consists of a path overhead POH located at the beginning of each row and having the length of one byte (9 bytes altogether), fixed stuff FS located at the following two columns, TU-3 pointers or a null pointer indicator NPI located at the following three columns, fixed stuff or VC-3 path overheads (VC-3 POH) located at the following three columns, and the actual payload section PL. The null pointer indicator NPI is used to separate the tributary unit groups T
REFERENCES:
patent: 4471479 (1984-09-01), Waas
patent: 5197063 (1993-03-01), Nakano et al.
patent: 5311506 (1994-05-01), Beisel
patent: 5351238 (1994-09-01), Ashi et al.
patent: 5416772 (1995-05-01), Helton et al.
Alatalo Hannu
Kokko Marko
Hsu Alpus H.
Nokia Telecommunications Oy
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