Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-03-31
2009-02-10
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07490308
ABSTRACT:
A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.
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Gonzalez Christopher J.
Gray Michael S.
Guzowski Matthew T.
Hibbeler Jason D.
Runyon Stephen I.
Cantor & Colburn LLP
International Business Machines - Corporation
Kotulak Richard
Whitmore Stacy A
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