Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2007-03-06
2007-03-06
Huynh, Kim (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S054000, C710S056000, C710S005000, C710S015000, C710S036000
Reexamination Certificate
active
10660033
ABSTRACT:
A method, apparatus and computer program product are provided for implementing dynamic Virtual Lane buffer reconfiguration in a channel adapter. A first register is provided for communicating an adapter buffer size and allocation capability for the channel adapter. At least one second register is provided for communicating a current port buffer size and one second register is associated with each physical port of the channel adapter. A plurality of third registers is provided for communicating a current VL buffer size, and one third register is associated with each VL of each physical port of the channel adapter. The second register is used for receiving change requests for adjusting the current port buffer size for an associated physical port. The third register is used for receiving change requests for adjusting the current VL buffer size for an associated VL.
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patent: 6816889 (2004-11-01), Graham
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Beukema Bruce Leroy
Fuhs Ronald Edward
Paynton Calvin Charles
Rogers Steven Lyn
Walk Bruce Marshall
Chen Alan S.
Huynh Kim
Pennington Joan
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