Method for implementing domino SRAM leakage current reduction

Details Method for implementing domino SRAM leakage current reduction Method for implementing domino SRAM leakage current reduction

2007-05-04

2008-08-19

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189110

Reexamination Certificate

active

07414878

ABSTRACT:
A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of local SRAM cell groups, receives precharge signals and provides an output connected to a global dot line. A sleep input is applied to SRAM sleep logic and a write driver including sleep control. Data true and data complement outputs of the write driver are forced to a respective selected level to discharge the bit lines and global dot lines when the sleep input transitions high. Discharging the bit lines and global dot lines is implemented through gating in the write driver without requiring any additional devices in the local evaluation circuit.

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Khellah et al., A 4.2Ghz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS, ISSCC 2006, pp. 624-625.

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