Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-11-15
2003-11-18
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S703000, C438S720000
Reexamination Certificate
active
06649526
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for implanting and coding a read-only memory with automatic alignment at four corners, which is especially used in a mask memory, wherein the isolating layer and spacing layer are used for implantation and coding so that the code areas are aligned automatically.
BACKGROUND OF THE INVENTION
Read-only memories are widely used in various digital devices, such as microcomputers, microprocessors, etc. for storing the fixing programs of these systems. Read-only memories are solid memories. In general, the customer sends programs to the memory manufacturing plant. Then the plant programs the programs into a read-only memory so as to be formed with a product which is then sent to the customer. The manufacturing process of read-only memory is very complex and many steps are necessary to be executed. Each step needs a great deal of time, which includes the process of manufacturing material and control of every factors. For most ROM parts, other than those stored in the programming, the other structures are identical. Therefore, the ROM is produced to a semi-product before programming for being stocked in advance. After being ordered by customers, optic masks are made. Then after programmed, it is sent to the customers so as to provide a preferred service. Therefore, the mask ROM after programmed is a general product in the industry.
However, in the prior art mask memory, it often occurs that the mask is misaligned. It can not be completely avoided in the manufacturing process of an integrated circuit. Furthermore, if in the process of the ion implantation in manufacturing a read-only memory, a misalignment occurs. Since the transversal diffusion of the implantation impurities, the adjacent memory cell will be closed. For example, initially, the cell is preset as an “ON” cell, or the adjacent cell is a lower read current. Especially for the memory cell far away from the voltage input point, the current is affected greatly.
Referring to
FIGS. 1 and 2
, a cross sectional view and an upper view of a prior art read-only memory is illustrated. As shown in the figures, the memory includes a transversal N source/drain region
10
which are bit lines and longitudinal polysilicon gate areas
12
, which are word lines. A channel
14
is formed between two adjacent bit lines
10
. Stacked gate oxide layer
16
and word lines
12
are arranged above the channel region
14
. In the programming process, by the photoresist layer
18
on the programming optic mask so as to expose the channel regions to be written, for example, the code areas
20
and
22
, wherein the code area
20
is not aligned, while the code area
22
is aligned. Next, the process of ion implantation is performed so that the memory cell is cut off forever. Therefore, object of writing code is achieved.
However, if the programming mask is misaligned, then the implanted ion will diffuse transversally and possibly enter into the adjacent memory cells so as to partly cut off to reduce the read current, even an error judgment occurs.
SUMMARY OF THE INVENTION
A primary object of the present invention is to provide a method for implanting and coding a read-only memory with automatic alignment at four corners for isolating each code area by each isolating layer and spacing layer so that as in implanting and coding, the code area can be aligned automatically.
In accordance with the object of this invention, a method for implanting and coding a read-only memory with automatic alignment at four corners for being used in a mask memory has been achieved. The method comprises the following steps. The shielding layer is etched back on the striped first polysilicon layers. A spacing layer is formed on the gate oxides and between the striped first polysilicon layers. A second polysilicon layer covers the spacing layer and the striped first polysilicon layers. The second polysilicon layer and the striped first polysilicon layers are etched until the gate oxides are exposed and the second polysilicon layer becomes a plurality of striped second polysilicon layers. An isolating layer is deposited on an etching portion of the striped first polysilicon layers and an etching portion of the striped second polysilicon layers. The striped second polysilicon layer acts as a mask and code areas are defined for performing the process of implantation and coding.
The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing.
REFERENCES:
patent: 4258378 (1981-03-01), Wall
patent: 5536669 (1996-07-01), Su et al.
patent: 5665621 (1997-09-01), Hong
patent: 5691216 (1997-11-01), Yen et al.
patent: 6251732 (2001-06-01), Hsu
patent: 6403424 (2002-06-01), Lee et al.
Chen Kin-Chan
Macronix International Co. Ltd.
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