Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-01-02
2004-08-24
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S013000
Reexamination Certificate
active
06782515
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to a method for optimizing the testing of integrated circuits (IC) and, more particularly, to a method for improving the test coverage by identifying additional test points for be inserted in the IC under test.
BACKGROUND OF THE INVENTION
Digital circuits are tested using a variety of strategies including functional test patterns, deterministic structural test patterns, and random patterns. Random pattern testing is particularly significant because it requires relatively little test data and can be accomplished not only by automated test equipment, but by the digital circuit itself using Built-in Self Test (BIST) circuitry. In order to achieve high random pattern testability, it is often necessary to modify a digital circuit design such that random patterns more easily detect potential defects in the IC under test.
One way of modifying digital circuits to improve random pattern testability is known as test point insertion. During test point insertion, additional logic and scannable latches are added to the logic to provide additional points of control or observation during testing. By way of example, and referring to
FIG. 1
, there is shown a random-resistant circuit, where the signal feeding the top input of the two input AND gate is nearly always 0 when random patterns are applied to the circuit, since the 16 input AND gate will produce a logic 1 only once every 216 random patterns. Such a path is rarely sensitized to allow faults to propagate through the bottom input of the downstream AND gate. Furthermore, faults in the downstream logic requiring a logic 1 for activation will be rarely be activated. If now, a control-1 test point is added to the circuit, the random pattern testability substantially improves.
Referring to
FIG. 2
, it is evident that adding an OR-gate driven by a scannable latch improves the probability that a logic 1 will appear on the top input to the 2-input AND gate, and will propagate to downstream logic to enable the detection of certain faults not otherwise tested. Additional faults will be allowed to propagate through the 2-input AND gate, and faults located in the downstream logic requiring a logic 1 for activation will have a much higher probability of being activated. This OR gate driven by a scannable latch is known as a control-1 test point. In other cases, a control-0 test point (implemented as an AND gate) or an observation point (implemented as a signal feeding a scannable latch) may be inserted. The problem being solved by this invention is to efficiently identify where test points should be inserted in the IC, and what type of test points should be added thereat.
Several solutions exist to the problem of test point identification. For instance, in an article by B. H. Seiss, P. M. Trouborst, and M. H. Schulz, “Test Point Insertion for Scan-Based BIST,” published in the
Proceedings of the European Test Conference
, pp. 253-262, 1991, a cost function gradient technique for inserting test points is described. This method is based on an earlier work by F. Brglez, published in the article “On Testability of Combinational Networks”,
Proceedings of International Symposium on Circuits and Systems
, pp. 221-225, 1984, and on work by R. F. Lisanke, A. J. Brglez, A. J. DeGeus, “Testability-Driven Random Test-Pattern Generation”, published in the
IEEE Transactions on CAD
, Vol. CAD-6, November 1987, pp. 1082-1087, all of which are based on random pattern testability. The method described in the aforementioned articles selects one test point at a time from a set of candidate test points, which is chosen according to a set of criteria that estimates the improvement in random pattern testability if the test point were inserted. Each candidate test point is temporarily incorporated in the circuit, and the actual improvement in random pattern testability is measured. Once all of the candidates have been evaluated, the test point providing the largest increase in random pattern testability is added to the circuit. This process is repeated until the maximum number of test points is achieved, or until the circuit reaches a satisfactory level of random pattern testability.
The test point insertion algorithm described in U.S. Pat. No. 6,256,759, “Hybrid Algorithm for Test Point Selection for Scan-Based BIST,” to S. K. Bhawmik, et al., improves the performance of the previously mentioned single test point insertion algorithm developed by Seiss et al. By recognizing that the effect of a test point is only significant in the area of logic immediately surrounding the test point, calculations used to determine the effect of a test point on random pattern testability can be reduced by considering only those nodes in the circuit for which the test point has a significant effect.
In U.S. Pat. Nos. 5,737,340 and 6,070,261, “Multi-phase Test Point Insertion for Built-in Self Test of Integrated Circuits”, both to N. Tamarapalli, et al., a method for inserting test points into a logic circuit is described, wherein test points are enabled or disabled depending on certain control signals. Each combination of control signals is known as a phase. Additional logic is added to the chip to decode the control signals and to control the operation of the test points. The algorithm for determining test points uses probabilistic fault simulation to determine test point locations rather than way of a COP (Controllability/Observability Program) based approach used in the previously described articles. However, as in previous cases, the test point insertion algorithm determines the added test points one at a time.
The process of test point insertion is further enhanced by considering signal propagation delays through the various paths in the logic circuit, as described in U.S. Pat. No. 5,828,828, “Method For Inserting Test Points for Full and Partial Scan Built-in Self Testing,” to Lin and Cheng. The insertion of a test point is disallowed if by doing so it introduces a signal delay that negatively impacts the performance of the circuit. In order to determine whether this situation occurs, the test point is assigned a delay value. For each node in the circuit, a signal slack is computed. (Note: signal slack is the amount of time by which a signal may be delayed before it must reach a specified node in the circuit). If the delay for the test point exceeds the signal slack for the node, the test point is prevented from being added to the node.
In U.S. Pat. No. 6,038,691, “Method Of Analyzing Logic Circuit Test Points, Apparatus for Analyzing Logic Circuit Test Points and Semiconductor Integrated Circuit with Test Points,” to Nakao et al., several refinements to the test point insertion process are described. A cell replacement approach reduces the signal delay and area overhead involved when inserting control test points. A control-1 test point is naturally described as a two-input OR gate inserted into a signal, wherein the other input is fed by a scannable latch or primary input. A control-0 test point is naturally described as a two-input AND gate inserted into a signal, wherein the other input is fed by a scannable latch or primary input. Rather than inserting additional gates into a logic circuit, Nakao et al., define a table of acceptable cell replacements such that the insertion of a control-0 or control-1 test point is achieved by replacing a library cell with a given number of inputs (and type) with another cell having a different number of inputs (and type). For example, if a control-1 test point is added to a signal feeding an inverter, the inverter can be replaced with a two input NOR gate. This process reduces both the area and the signal delay imposed by insertion of test points.
An unacceptable signal delay is further reduced by the use of a table that describes paths and/or nodes or hierarchical entities in the circuit where insertion of test points is not allowed because there is insufficient slack in the path to allow additional logic gates to be inserted. Nodes in the circuit are not considered test point candid
Khoja Faisal R.
Scott David G.
Cadence Design Systems Inc.
Garbowski Leigh M.
Orrick Herrington & Sutcliffe
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