Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-03-07
2006-03-07
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07010765
ABSTRACT:
An integrated circuit design includes a description of a net for distributing a signal from a root node to one or more leaf nodes downstream of the root node. Some segments of the net include inverters and some segments branch into other segments. The IC design is processed to determine a maximum number of inverters that can be removed from the net without affecting a logic state of the signal as it arrives at the leaf nodes. For each segment of the net other than segments terminating on root or leaf nodes two corresponding data sets are generated: one data set indicates a maximum number of inverters that may be removed downstream of its corresponding segment without altering the logic state of the signal at any downstream leaf node, and the other data set indicates a maximum number of downstream inverters that may be removed that will alter the logic state of the signal arriving at every downstream leaf node. Each data set points to all data sets corresponding to segments immediately downstream of the data set's corresponding segment, so that the data sets for all segments form a decision tree that may be traversed to determine which inverters must be removed to maximize the number of inverters removed from the net without affecting the logic state of the signal arriving at each leaf node.
REFERENCES:
Jain et al., “Inverter Minimization in Multi-Level Logic Networks”, Nov. 1993, IEEE/ACM International Conference on Computer-Aided Desig, Digest of Technical, pp. 462-465.
Kao Wei-Lun
Liu I-Min
Cadence Design Systems Inc.
Lin Sun James
Rosenberg , Klein & Lee
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