Method for identifying memory bit cells and connections

Static information storage and retrieval – Addressing – Multiple port access

Reexamination Certificate

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Details

C365S049100, C365S189011, C365S201000, C716S030000

Reexamination Certificate

active

07570539

ABSTRACT:
A method for identifying memory bit cells and connections for analysis of a circuit block. The method includes defining a bit pattern for each bit cell node in a bit cell. The method also includes defining a node pattern for each node in the circuit block; and matching the node patterns with the bit patterns. The bit cells and corresponding bit line connections and word line connections in the circuit block are determined based on matches found during the matching.

REFERENCES:
patent: 6112022 (2000-08-01), Wei
patent: 6374205 (2002-04-01), Kuribayashi et al.
patent: 7139204 (2006-11-01), Behera

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