Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-07-12
2008-01-15
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S108000, C714S714000, C714S030000, C714S037000, C324S501000, C324S527000
Reexamination Certificate
active
07320115
ABSTRACT:
A method is disclosed for identifying a physical failure location on an IC without using layout-versus-schematic (LVS) verification tool. In the method, the integrated circuit is tested with one or more test patterns to identify a failure port thereon. Hierarchical information of the failure port is generated through the test patterns. A physical location of the failure port in a layout of the integrated circuit is identified through a relation between the hierarchical information and a floor plan report. Layout information of a routing path associated with the physical location of the failure port is retrieved from a layout database.
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K & L Gates LLP
Kik Phallaka
Taiwan Semiconductor Manufacturing Co. Ltd.
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