Method for heat treatment of silicon wafers and silicon wafer

Metal treatment – Barrier layer stock material – p-n type

Reexamination Certificate

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Details

C257SE23080, C257SE31131, C438S974000

Reexamination Certificate

active

07011717

ABSTRACT:
According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1–60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104defects/cm3or more in a wafer bulk portion, a crystal defect density of 1.0×104defects/cm3or less in a wafer surface layer of a depth of 0.5 μm from the surface, a crystal defect density of 0.15 defects/cm2or less on a wafer surface and surface roughness of 1.0 nm or less in terms of the P-V value. By these, crystal defects in wafer surface layers can be reduced by a simple method with a small amount of hydrogen used without degrading microroughness of wafers.

REFERENCES:
patent: 4378269 (1983-03-01), Matoushita et al.
patent: 4467042 (1984-08-01), Hatta et al.
patent: 4554425 (1985-11-01), Kashiwagi et al.
patent: 5968264 (1999-10-01), Iida et al.
patent: 6136684 (2000-10-01), Sato et al.
patent: 6147014 (2000-11-01), Lyding et al.
patent: 6191009 (2001-02-01), Tamatsuka et al.
patent: 6217650 (2001-04-01), Hirose et al.
patent: 6245311 (2001-06-01), Koboyashi et al.
patent: 6254672 (2001-07-01), Falster et al.
patent: 6531416 (2003-03-01), Kobayashi et al.
patent: 60-247935 (1985-12-01), None
patent: 61-193458 (1986-08-01), None
patent: 62-123098 (1987-06-01), None
patent: 2-248051 (1990-10-01), None
patent: 4-167433 (1992-06-01), None
patent: 5-144827 (1993-06-01), None
patent: 5-218053 (1993-08-01), None
patent: 5-308076 (1993-11-01), None
patent: 6-196459 (1994-07-01), None
patent: 6-252154 (1994-09-01), None
patent: 06-295912 (1994-10-01), None
patent: 6-349839 (1994-12-01), None
patent: 07-161707 (1995-06-01), None
patent: 7-235507 (1995-09-01), None
patent: 7-235534 (1995-09-01), None
patent: 7-321120 (1995-12-01), None
patent: 08-162461 (1996-06-01), None
patent: 08-264549 (1996-10-01), None
patent: 08-264552 (1996-10-01), None
patent: 10-79364 (1998-03-01), None
patent: 10-326790 (1998-12-01), None
patent: 11-354529 (1999-12-01), None
S. Yamakawa et al., “Study of interface roughness dependence of electron mobility in Si inversion layers using the Monte Carlo method,”American Institute of Physics, Jan. 1996, vol. 79, pp. 911-916.

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