Method for hardening gate oxides using gate etch process

Details Method for hardening gate oxides using gate etch process Method for hardening gate oxides using gate etch process

2003-01-24

2004-06-29

Lee, Hsien Ming (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S588000, C438S655000, C438S657000, C438S663000, C438S664000

Reexamination Certificate

active

06756291

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to CMOS device fabrication processes and, more particularly, to a method of manufacturing gate structures having an improved resistance to hot carrier induced defects at the silicon/gate oxide interface thereby improving electrical properties including current voltage characteristics of an MOS transistor.
BACKGROUND OF THE INVENTION
Fabrication of a metal-oxide-semiconductor (MOS) integrated circuit involves numerous processing steps. A gate dielectric, typically formed from silicon dioxide, is formed on a semiconductor substrate which is doped with either n-type or p-type impurities. For each MOS field effect transistor (MOSFET) being formed, a gate electrode is formed over the gate dielectric, and dopant impurities are introduced into the semiconductor substrate to form source and drain regions. Many modern day semiconductor microelectronic fabrication processes form features having less than a 0.25 line width. As feature size decreases, the size of the resulting transistor as well as transistor features also decrease. Fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single die area.
In semiconductor microelectronic device fabrication, polysilicon and silicon dioxide (SiO
2
) are commonly used to respectively form gate electrodes and gate dielectrics for metal-oxide-semiconductor (MOS) transistors. As device dimensions have continued to scale down, the thickness of the SiO
2
gate dielectric layer has also decreased to maintain the same capacitance between the gate and channel regions. A problem with using SiO
2
as the gate dielectric is that thin SiO
2
oxide films tend to accumulate lattice damage in the gate oxide leading to degraded electrical performance. Frequently, during reliability testing, the gate structure including the gate electrode and gate oxide are subjected to high electric fields to induce hot carrier damage in the gate oxide to determine the reliability of the MOSFET devices.
For example, high stress voltage conditions are frequently created in the silicon substrate between the source and drain regions during device operation causing the charge carriers to gain sufficient energy to create impact-ionized electron-hole pairs, the charge carriers also referred to as hot carriers. A fraction of the hot carriers will have sufficient energy to overcome the silicon/gate oxide barrier and be injected into the gate oxide causing the creation of interface states and charge trapping states in the gate oxide. Such gate oxide damage causes a gradual degradation of the MOSFET's current-voltage characteristics. The degradation, for example, causes circuit switching characteristics and threshold voltages to change over time.
For example, one type of damage caused during hot carrier stressing, is the formation of interface states. For example, at the Si/SiO2 interface in an ideal interface region all the bonds are saturated, for example, bonded to another silicon atom, an oxygen atom, or a hydrogen atom. Hot carriers injected across the Si/SiO2 interface can cause the chemical bonds to break forming what are referred to as dangling bonds. Dangling bonds cause a disruption in the periodicity of the lattice and undesirably affect the electrical properties of the gate oxide. For example, an Si—H bond has a bonding energy of about 3.18 eV which is broken by a hot carrier having a greater energy. One effect of such interface state damage is the decrease of what is known as the sub-threshold voltage gradient.
Several approaches to hardening the gate oxide to resist hot carrier induced damage have included adding nitrogen to the gate oxide by a variety of processes including nitrogen implantation and nitridation of either the silicon or gate oxide (SiO
2
) followed by annealing treatments to distribute the nitrogen to the Si—SiO interface. Nitrogen is believed to suppress hot carrier induced damage by becoming incorporated into the oxide at the Si/SiO
2
oxide interface. Several problems have emerged with doping the gate oxide with nitrogen including creating electron trapping states and decreasing the charge carrier mobility in the gate oxide.
Another approach has been to dope the gate oxide with fluorine. For example it is known that fluorine can form stronger bonds (e.g., 5.73 eV) compared to Si—O, Si—Si, or Si—H bonds, thereby resisting hot carrier induced damage. Fluorine, for example has been implanted by ion implantation into the polysilicon gate electrode followed by an annealing process to diffuse the fluorine into the gate oxide region. A problem with this approach is that the polysilicon gate electrode is typically additionally doped with, for example, boron or phosphorous, to adjust the polysilicon electrical properties. The addition of fluorine to the polysilicon has had the detrimental effect of increasing the diffusion of implanted species, for example, boron into the gate oxide and silicon substrate thereby detrimentally affecting MOS transistor electrical properties. Fluorine has also been implanted by ion implantation into the gate oxide followed by an annealing process. One problem with this approach is that the problem of boron penetration through the gate oxide is not alleviated. Another problem is the equipment intensive and time intensive nature of ion implantation.
Therefore it would be advantageous to develop an improved method for formation hot carrier hardened gate oxides where the gate oxide is better able to resist hot carrier induced defects to improve MOS device performance and reliability.
It is therefore an object of the invention to provide an improved method for formation hot carrier hardened gate oxides where the gate oxide is better able to resist hot carrier induced defects to improved MOS device performance and reliability while overcoming other shortcomings and deficiencies of the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for repairing a damaged gate oxide layer while making the gate oxide layer resistant to gate oxide degradation.
In a first embodiment, the method includes providing a silicon substrate having an overlying gate oxide layer and a polysilicon layer overlying the gate oxide layer; forming a polycide layer over the polysilicon layer; photolithographically patterning the polycide layer for dry etching a gate structure; dry etching a gate structure including etching through a thickness of the polycide layer including a fluorine containing etching chemistry to produce implanted fluorine in the polycide layer; and, thermally annealing the silicon substrate-including the gate structure to thermally diffuse the implanted fluorine to an interface region of the gate oxide and the silicon substrate to form chemical bonds with silicon.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.


REFERENCES:
patent: 5135608 (1992-08-01), Okutani
patent: 6191463 (2001-02-01), Mitani et al.
patent: 6417104 (2002-07-01), Hu
patent: 6537910 (2003-03-01), Burke et al.
patent: 2003/0139061 (2003-07-01), Jeng et al.

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