Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-08-07
2003-02-25
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C702S121000, C700S113000
Reexamination Certificate
active
06526545
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for testing a semiconductor wafer, and particularly to a method for generating a test sub-program to test a semiconductor wafer automatically.
BACKGROUND OF THE INVENTION
Electrical testing in the wafer level is becoming more and more important during the complicated semiconductor circuit processing. For example, the cost for semiconductor post-processes such as package and testing are becoming higher. Accordingly, it is best to reflect the real situation and eliminate abnormal wafers during the wafer level electrical testing to save money. Moreover, the cycle time of the semiconductor processes is longer nowadays, and the wafer level electrical testing can also reflect the quality of on-processing wafers to minimize the wasting of time. Besides, the wafer level electrical testing procedures can be used to monitor and detect the correlation of complicated semiconductor processes. In other words, the importance of the wafer level electrical testing includes the yield rate monitoring, extraction of the processing parameters and tools for process development.
Nevertheless, during the hundreds of (maybe thousands of) processing steps in the semiconductor production lines, the in process testing (or the semiconductor's parameter testing) is one of the major concerns of a semiconductor factory to evaluate the process capability and productivity. The process tests include items such as the isolation test, the junction leakage test or resistance measurement (such as contact resistance or sheet resistance), the device test items such as the threshold voltage measurement of a complementary metal oxide semiconductor (CMOS) integrated circuits, the saturated drain current l
dsat
of a CMOS, or the mobility of the electrons in a device . . . etc. All of the described test items are included in the wafer acceptance test (WAT) to evaluate the processes and devices respectively.
During the development of a new semiconductor technology, the developer should design a lot of electrical testing procedures to ensure the reliability and quality of the processes or devices. For example, the developer will produce a lot of test key patterns according to this new semiconductor technology or product design in order to acquire the parameters of processes or devices. It is also possible for a developing process to design a new photomask for test key patterns and evaluate the processes before mass production. When conducting the electrical function tests of the integrated circuits, for example, to check all the designed specifications of the CMOS device, the developer should develop automatic testing programs according to the characteristics of the parameters of processes and devices. However, the testing program of the test items and test quantities is changed due to the different requirements. Therefore, the programmer should spend a lot of effort and time to rewrite the programs even if they deal with the same test items or test plan.
For this reason, it is a waste of time and not efficient to develop many similar programs just because of the variety of testing requirements. Furthermore, there is a need in the fast developing semiconductor technology for a testing field in order to achieve a better management of the programs, better quality control and for cost savings.
SUMMARY OF THE INVENTION
The present invention responds to the need for a parameter testing program for distinct semiconductor processes and devices during the wafer level parameter testing, specifically in the development of a new semiconductor technology. Time spent for rewriting the programs and management of all the testing programs have perplexed the programmer. Therefore, the main object of the present invention is to develop a method for generating a wafer level parameter testing program automatically.
Another object of the present invention is to use the method for generating the wafer level parameter testing program to fit the requirement of the future expansion for different technologies of the semiconductor industry.
Still another object of the present invention is to use the method for generating the wafer level parameter testing program to make an efficient maintenance and management of the testing field.
According to the above objects, the summary of the present invention is as follows:
Firstly, a test key database describing the test items and locations of the test patterns have to be completed by a developer, wherein the format and title of the database is related to the process parameter database, device type database, and device parameter database. Subsequently, the user selects the test items according to the test key database and creates a test plan, then inputs to the controlling program (herein referred to as auto program generator, APG). The APG program will check the data format of the test plan and display an error message when the format is not correct. The APG program will take out the test items one by one if the input data format is correct.
Thereafter, the APG program will find out the test condition parameters according to the processes and devices, such as the data from the test sub-program database, or from the process parameter database when it belongs to the process test items and/or from the device parameter database when it belongs to the device test items. After all the test condition parameters of test items in the test plan are collected, the APG program will create a optimized test program. The “optimized” test program is sorted according to the efficiency or for the purpose of test protection, such as the minimum movement of the probe or the lower voltage tested in advance. Afterward, the main WAT (wafer acceptance test) program uses this test program as a sub-program and proceeds the testing to evaluate the processes and devices.
By using the APG program to generate the test programs automatically, the new technology's developer does not have to rewrite the test program but only has to maintain the input tables (i.e., databases) of the APG program. In addition, the optimized creating flow path of the APG program can provide the best quality for testing and reduce the human error. Besides, the expandable databases can also be used in future generations.
REFERENCES:
patent: 5148379 (1992-09-01), Konno et al.
patent: 5668745 (1997-09-01), Day
patent: 6075930 (2000-06-01), Yamane et al.
patent: 6314332 (2001-11-01), Kida
Lin Geeng-Lih
Lo Shien-Wang
Powell Goldstein Frazer & Murphy LLP
Rossoshek Helen B
Siek Vuthe
Vanguard International Semiconductor Corporation
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