Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-10-22
2003-11-18
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06651227
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to logic delay test methodology, and more specifically, to circuit design techniques and methods related to test pattern generation.
BACKGROUND OF THE INVENTION
Verifying correct circuit operation of digital logic circuits at their full speed clock rate remains an important activity for semiconductor manufacturers when testing integrated circuits. Static tests that assume and verify fixed logic states at predetermined test nodes are useful in verifying functionality of logic circuitry, but such tests do not verify proper operation at the system clock speed. When circuitry is operating at the system clock speed, some logic circuit signals may not propagate in time to be latched by output latches or internal latches. Defect mechanisms such as cross-talk, process variations, ground bounce, etc., affect circuit functionality by introducing delays. Such timing failures result in system failure. Failures that cause logic circuitry to malfunction at desired clock rates are known as delay faults. Therefore the purpose of delay testing is to verify that a circuit design operates correctly at a specific clock speed.
Two fault models that have been proposed for testing delay faults are the transition fault model and the path delay model. The path delay model assumes that a delay will manifest itself on a specific path of the circuit. As a result, there are a very large number of paths to test. The transition fault model assumes a gross delay, i.e., gate delay faults manifest themselves on all paths passing through the fault site. Hence, sensitizing any path that passes by the fault site is enough to detect the fault. The transition fault model requires pairs of vectors as test vectors. Two common methods to generate a transition fault test for scan-based designs are known as a skewed-load method and a broad-side method. In the skewed load test, a scan latch is loaded with a test pattern or vector from a tester. The first pattern sets up an initialization value for the logic to be tested. A second pattern or vector is a one-bit shift over the first pattern or vector and is also provided by the tester. The second pattern or vector must be sequentially clocked through the scan latch and needs to have a value that provokes a desired transition at the site of the fault. The effect of the transition is propagated to a primary output or to an observe point (i.e. a scan latch). Because the second pattern represents a one-bit shift over the first pattern, the second pattern may not readily provide a needed value to obtain the desired transition. The result is that there may be loss of coverage in testing certain delay faults by using the skewed-load test. Also, the skewed-load model requires the shift clock of the scan latch to operate at system speed. In most circuits, the scan clock of scan latches operates at a much slower speed due to performance and area factors of the scan latch design. As a result, the skewed-load test has a speed restraint. Additionally, the vector pairs that can be applied by skew-load testing might activate certain transactions that are impossible to activate functionally.
In the broad-side method, the second vector is not scanned from a tester, but rather is generated from the response of the design block driving the combinational circuitry being tested. Therefore, detailed knowledge of the circuitry in the driving block is required in order to know what inputs are required to generate a desired output value. The broad-side method requires two cycles of sequential processing and this method has limited capability to generate a rich set of two-pattern tests. The sequential processing of the broad-side method results in less than optimal fault coverage using commercially available automated test pattern generation (ATPG) tools. The two time-frame sequential processing is difficult for many commercially available ATPG tools and results in long run times and low coverage.
REFERENCES:
patent: 5138619 (1992-08-01), Fasang et al.
patent: 5278842 (1994-01-01), Berry, Jr. et al.
patent: 5642362 (1997-06-01), Savir
patent: 5657292 (1997-08-01), McClure
patent: 5978944 (1999-11-01), Parvathala et al.
W.H.McAnney and J. Savir, Latch-To-Latch Delay Testing in LSSD Using a Three-Latch SRL, Oct. 1988 IBM Technical Disclosure Bulletin, 1997—2001 Delphion Inc., pp. 89-95.
Melvin A. Breuer et al., “Diagnosis & Reliable Design of Digital Systems”, 1976 Computer Science Press, Inc., Chapter 3 “Test Generation For Sequential Circuits”, pp. 90-105.
B. Konemann et al., “Delay Test: The Next Frontier for LSSD Test Systems”, 1992 IEEE International Test Conference, Paper 30.3, pp. 578-587.
Alfred L. Crouch, “Design for Test for Digital IC's and Embedded Core Systems”, pp. 72-75.
Jacob Savir et al., “On Broad-Side Delay Test”, IBM Microelectronics Division, 1994, IEEE Transaction on CAD of ICS, pp. 284-290.
Carol Pyron et al., DFT Advances in Motorola's MPC7400, a PowerPC™ Microprocessor, 1999 IEEE, Paper 62, pp. 137-146.
Jacob Savir et al., “Scan-Based Transition Test”, Aug., 1993 IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 8, pp. 1232-1241.
Nandu Tendolkar et al., “At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC™ Microprocessor”, IEEE VTS, 2000, 6 pgs.
Abadir Magdy S.
Zhu Juhong
Chiu Joanna G.
Do Thuan
King Robert L.
Motorola Inc.
Smith Matthew
LandOfFree
Method for generating transition delay fault test patterns does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for generating transition delay fault test patterns, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for generating transition delay fault test patterns will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3138202