Method for generating timing constraints of logic circuit

Details Method for generating timing constraints of logic circuit Method for generating timing constraints of logic circuit

2007-07-24

2007-07-24

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C703S016000

Reexamination Certificate

active

11121083

ABSTRACT:
In hierarchical design of a logic circuit by utilizing lower-level blocks of the logic circuit, data on the logic circuit with the hierarchical structure, library data holding primitive information on the logic circuit and timing constraints on the lower-level blocks are input at a data input step. Based on these input data, it is determined whether or not interface specifications of timing constraints on the lower-level blocks match each other at a matching determination step before a constraint converting step of converting the timing constraints on the lower-level blocks into a timing constraint on a higher-level block. Accordingly, it is possible to avoid generation of an excessively reduced or rigorous timing constraint on the higher-level block resulting from mismatching between interface specifications of timing constraints on the lower-level blocks.

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Drissi et al., “Submodule Construction for Timed Systems”, Proceedings of the 41st IEEE Conference on Decision and Control, vol. 1, Dec. 10-12, 2001, pp. 28-33.

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