Method for generating prefetch instruction with a field specifyi

Details Method for generating prefetch instruction with a field specifyi Method for generating prefetch instruction with a field specifyi

1997-08-22

1998-08-18

Lall, Parshotam S.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711123, 711122, 711141, G06F 1208

Patent

active

057969710

ABSTRACT:
Disclosed is a method and system for providing for the prefetching of data or instructions. A prefetch instruction which is in an instruction stream is processed by memory management unit (MMU) where prefetch cache control information is placed as part of the already existing prefetch instruction. Once processed by the MMU, the prefetch instruction thus contains binary fields allowing the operating system or runtime software to control cache prefetching by assigning values to the binary fields which provide the optimal cache set location and the optimal amount of data to be prefetched and thus reduces thrashing.

REFERENCES:
patent: 5307477 (1994-04-01), Taylor et al.
patent: 5317718 (1994-05-01), Jouppi
patent: 5537573 (1996-07-01), Ware et al.
patent: 5551001 (1996-08-01), Cohen et al.
Hwang et al. (Computer Architecture and Parallel Processing) McGraw-Hill Co. pp. 102-107, 1984.

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