Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Layout editor
Reexamination Certificate
2011-08-09
2011-08-09
Chu, Chris (Department: 2815)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Layout editor
C716S055000, C716S126000, C430S005000
Reexamination Certificate
active
07996813
ABSTRACT:
A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.
REFERENCES:
patent: 5948573 (1999-09-01), Takasahi
patent: 6225697 (2001-05-01), Iguchi
patent: 6253362 (2001-06-01), Anand et al.
patent: 6261883 (2001-07-01), Kobuchi et al.
patent: 7844080 (2010-11-01), Itoh
patent: 2001/0042921 (2001-11-01), Mori et al.
patent: 2002/0061608 (2002-05-01), Kuroda et al.
patent: 2003/0014725 (2003-01-01), Sato et al.
patent: 2005/0086626 (2005-04-01), Sato et al.
patent: 2006/0097399 (2006-05-01), Hatano et al.
patent: 2008/0003510 (2008-01-01), Harazaki
patent: 2010/0138801 (2010-06-01), Matsuoka et al.
patent: 2011/0023003 (2011-01-01), Su et al.
patent: 63-025952 (1988-02-01), None
patent: 04-218918 (1992-08-01), None
patent: 09-321044 (1997-12-01), None
patent: 11-297817 (1999-10-01), None
patent: 2002-134618 (2002-05-01), None
patent: 2004-88102 (2004-03-01), None
patent: WO 01/63673 (2001-08-01), None
Okazaki et al., “‘Sea of Kelvin’ Multiple-pattern arrangement interconnect characterization for Low-k/Cu dual damascene and its findings,” IITC 2004 Proceedings (2004), pp. 211-213.
Notification of Reasons for Refusal mailed by the Japanese Patent Office on Jul. 14, 2009, for Japanese Application No. P2005-321571, and English-language translation thereof.
Fujimaki Takeshi
Hatano Masaaki
Higashi Kazuyuki
Kaneko Hisashi
Matsunaga Noriaki
Chu Chris
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
LandOfFree
Method for generating pattern, method for manufacturing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for generating pattern, method for manufacturing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for generating pattern, method for manufacturing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2666932