Method for generating non-blocking delayed clocking signals for

Details Method for generating non-blocking delayed clocking signals for Method for generating non-blocking delayed clocking signals for

1997-06-30

1999-11-09

Heckler, Thomas M.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 96, G06F 104, H03K 1900

Patent

active

059830131

ABSTRACT:
A method for generating non-blocking multiple-phase clocking system for use with domino-type dynamic logic includes receiving a primary clock signal and generating several delayed phases of the received primary clock signal. The number of clock phases equals the number of dynamic logic gates in the circuit. The method provides a first clock phase to the first dynamic logic gate of the circuit, a second clock phase to the second dynamic logic gate and so on. A timing analysis is performed of each logic path in the circuit to determine the arrival time of each critical input signals to each dynamic logic gate. The delay between adjacent clock phase is then predetermined so that each dynamic logic gate enters its evaluation phase before the critical input signal(s) to the particular dynamic logic gate arrives. This adjustment of the clock phases maximizes the logic evaluation speed of the dynamic logic circuit.

REFERENCES:
patent: 3935474 (1976-01-01), Komarek
patent: 5295164 (1994-03-01), Yamamura
patent: 5434520 (1995-07-01), Yetter et al.
patent: 5517136 (1996-05-01), Harris et al.
patent: 5578946 (1996-11-01), Carberry et al.
patent: 5751665 (1998-05-01), Tanoi

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