Method for generating mask data, mask and computer readable...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C430S005000

Reexamination Certificate

active

06560765

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for generating mask data, a mask, a computer readable recording medium, and more particularly a method for generating mask data, a mask, a computer readable recording medium, for forming trench isolation regions.
2. Description of Related Art
With the miniaturization of semiconductor devices (for example, MOS transistors) promoted in recent years, a further miniaturization of element isolation regions in semiconductor devices is required. In order to achieve a further miniaturization of element isolation regions in semiconductor devices, a trench isolation technique has been introduced. In the trench isolation technique, trenches are provided between semiconductor elements in a semiconductor substrate, and a dielectric material is filled in the trenches to isolate the semiconductor elements from one another. One example of the element isolation technique will be described below.
FIGS.
18
(
a
)-
18
(
c
) show in cross-section steps of forming trench isolation regions using a conventional trench isolation technique.
FIG.
18
(
a
) shows a silicon substrate
110
having trenches
116
, and a dielectric layer
121
formed over the silicon substrate
110
. A polishing stopper layer
114
is formed over effective convex regions
130
of the silicon substrate
110
. A pad layer
112
is interposed between the effective convex regions
130
and the polishing stopper layer
114
.
As shown in FIG.
18
(
b
), the dielectric layer
121
is planarized using the polishing stopper layer
114
as a stopper. The planarization of the dielectric layer
121
is performed by a chemical-mechanical polishing method (hereinafter referred to as a “CMP method”).
Then, as shown in FIG.
18
(
c
), the polishing stopper layer
114
is removed to thereby form trench dielectric layers
120
, whereby trench isolation regions
124
are completed.
However, as shown in FIG.
18
(
b
), a device design may require that plural effective convex regions
130
are closely formed in one area and an isolated effective convex region
130
is formed separated from such area. In this case, the following problems occur.
When the dielectric layer
121
is planarized by the CMP method, the polishing stopper layer
114
at the isolated effective convex region
130
may be excessively cut. On the other hand, the polishing stopper layer
114
on the densely formed effective convex regions
130
may not be cut enough as compared to the polishing stopper layer
114
at the isolated effective convex region
130
. This phenomenon occurs because the polishing rate differs depending on pattern densities of the effective convex regions
130
. In other words, a polishing pressure is concentrated on the polishing stopper layer
114
at the isolated effective convex region
130
. As a result, the polishing rate at the isolated effective convex region
130
becomes greater than the polishing rate at the densely formed effective convex regions
130
. Consequently, the polishing stopper layer
114
at the isolated effective convex region
130
is excessively polished.
When the polishing stopper layer
114
at the isolated effective convex region
130
is excessively polished, the thickness of the resultant trench dielectric layer
120
becomes irregular, as shown in FIG.
18
(
c
). Also, the polishing stopper layer
114
cannot properly perform its function. Moreover, as the isolated effective convex region
130
is excessively polished, the polishing cloth warps, and erosion occurs in the polishing stopper layer
114
in the area where the effective convex regions
130
are densely formed. The erosion is a phenomenon in which a corner section
114
a
of the polishing stopper layer
114
is cut. Also, when the polishing cloth warps, dishing occurs in an upper portion of the dielectric layer
121
. The dishing is a phenomenon in which an upper portion of the dielectric layer
121
is formed in a dish shape.
In order to solve the problems described above, one technique, in which dummy convex regions
132
are formed in the trench
116
, as shown in
FIG. 19
, is proposed. By the provision of the dummy convex regions
132
, the polishing pressure is distributed on the dummy convex regions
132
. Accordingly, the concentration of the polishing pressure on the isolated effective convex region
130
is prevented, and the polishing rate at the same region does not become excessively greater. Consequently, by the provision of the dummy convex regions
132
, the isolated effective convex region
130
is prevented from being excessively cut.
The technique for forming the dummy convex regions
132
is described in Japanese laid-open patent application HEI 9-107028, Japanese laid-open patent application HEI 9-181159, Japanese laid-open patent application HEI 10-92921, Japanese laid-open patent application HEI 11-26576, U.S. Pat. No. 5,885,856 and U.S. Pat. No. 5,902,752.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for generating mask data, a mask, and a computer readable recording medium, which are used for forming dummy convex regions in a specified pattern in a trench isolation region.
(A) In accordance with a first embodiment of the present invention, a method is provided for generating mask data that is used for a manufacturing method for a semiconductor device. The semiconductor device has a trench isolation region, provided in a semiconductor substrate, defining a row direction and first virtual linear lines extending in a direction that traverses the row direction, and a plurality of dummy convex regions provided in the trench isolation region, wherein the row direction and the first virtual linear lines define an angle of 2 to 40 degrees, and the dummy convex regions are disposed on the first virtual linear lines. The method may include the steps of:
(a) setting a restriction region pattern that defines a restriction region;
(b) setting dummy patterns that define the dummy convex regions; and
(c) mixing the restriction region pattern and the dummy patterns, wherein the dummy patterns that at least partially overlap the restriction region pattern are entirely excluded.
The “row direction” used here refers to one direction that is virtually defined in consideration of, for example, a restriction region.
In accordance with the present invention, for example, the following two effects are achieved.
(1) In accordance with the first embodiment of the present invention, the dummy patterns are set such that the dummy convex regions are disposed on the first virtual linear lines. The row direction and the first virtual linear lines define an angle of 2 to 40 degrees. In other words, the dummy patterns are set such that adjacent ones of the dummy convex regions formed on the first virtual linear lines and disposed next to one another in the row direction are mutually offset in a column direction. Accordingly, the adjacent dummy patterns disposed in the row direction are mutually offset in the column direction. As a result, in step (c), the dummy patterns can be readily set at a high level of density in an area adjacent to a restriction region pattern that extends in the row direction. In other words, even when some of the dummy patterns overlap the restriction region pattern, the other dummy patterns are securely generated in an area adjacent to the restriction region pattern. As a consequence, dummy patterns can be securely provided in a region where a gap between adjacent restriction region patterns is narrow. As a result, the following effects are achieved.
When dummy convex regions are formed in a trench, the dummy convex regions can be securely disposed in an area adjacent to the restriction regions. As a consequence, when the dielectric layer filled in the trench is polished, the polishing pressure is securely distributed on the dummy convex regions adjacent to the restriction region.
(2) Also, in accordance with the present invention, the dummy patterns that at least partially overlap the restriction region pa

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