Method for generating layouts by chamfering corners of polygons

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

10857822

ABSTRACT:
A method for generating a layout of a semiconductor circuit to satisfy minimum spacing requirements that includes generating one or more polygons for the layout, with each generated polygon having an area, a plurality of corners and satisfying the minimum spacing requirements of the layout rules. The corners of the generated polygon are then chamfered, and the generated polygon with chamfered corners is expanded or reduced in size.

REFERENCES:
patent: 5412239 (1995-05-01), Williams
McGrath et al., “Design Integrity and Immunity Checking: A New Look at Layout Verification and Design Rule Checking”, 1980, ACM, pp. 263-268.
Cadence Design Systems, Inc., Diva® Reference Manual, Jun. 2000, pp. 189-201.

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