Method for generating internal clock of semiconductor memory...

Details Method for generating internal clock of semiconductor memory... Method for generating internal clock of semiconductor memory...

2002-01-07

2003-06-10

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

06577175

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device and a method for internal clock generation and, more particularly, to a device and method for generating an internal clock synchronized with an external clock.
2. Description of the Related Art
In a typical electronic system, a central processing unit (CPU) and a semiconductor memory are interconnected through a signal bus. Typically, the CPU operates as a master, and the semiconductor memory operates as a slave. The CPU transmits data such as addresses, commands, and writing data, and a clock for sampling the data to the semiconductor memory.
An external clock signal transmitted through the signal bus may be synchronized with or centered to data as shown in
FIGS. 1A and 1B
, respectively. The memory as a slave receives the external clock signal to generate a data sampling clock as an internal clock signal, which should be transitioned with the triggering edge around the center of data signals as shown in FIG.
1
B. If the external clock signal is synchronized with the data, it is delayed to generate an internal clock signal centered about the data signal.
If an external clock signal is centered on or synchronized with data, the memory as a slave uses an internal clock signal adapted to a data valid window for sampling externally applied data. As the data rate increases, the data valid window becomes smaller. If the data and the clock signal have slightly different paths in the system, the skew between the clock signal and the data pins applied to the memory may further increase. In the case of DDR (double data rate) memories, in which data are clocked at both transactions within a clock cycle as shown in
FIG. 2A
, a large skew results in false clocking of data.
Therefore, a need exists for a semiconductor memory system having a function to selectively alter the timing of a clock signal to generate a data sampling clock signal as an internal clock signal which maximizes the data clocking data window, essentially as shown in FIG.
3
.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the aforementioned problems and provide a method for generating an internal clock and related circuit thereof.
It is another object of the present invention to provide a method for generating an internal clock and the related circuit thereof for making an accurate sampling of data even if there is a skew between the clock and data applied to a semiconductor memory.
It is a still another object of the present invention to provide a method for generating an internal clock and the related circuit thereof, in which delay time is controlled by an external code.
To accomplish the aforementioned objects in accordance with an aspect of the present invention, there is provided an internal clock generating circuit comprising:
a receiver for receiving an external clock;
a delay compensation circuit for taking an output clock of the receiver and delaying it by as much as the compensation delay time and control delay time subtracted from the cycle of the external clock;
an external control delay unit for delaying an output of the delay compensation circuit by as much as the sum of the control delay time and unit increase/decrease delay time in response to an external control code; and
an internal clock driver for driving an output of the external control delay unit and generating an internal clock centered about an externally applied data, thereby performing an accurate timing control to an external clock without any loss of performance.
In accordance with another aspect of the present invention, there is provided a method for generating an internal clock comprising the steps of:
delaying an external clock output through the receiver by as much as the compensation and control delay time is subtracted out of the cycle of the external clock;
delaying the output of the delay compensation circuit by as much as the control delay time and unit increase/decrease delay time are added in response to a digital control code; and
driving the output generated in the delaying step as an internal clock.


REFERENCES:
patent: 5349612 (1994-09-01), Guo et al.
patent: 5400370 (1995-03-01), Guo
patent: 6229364 (2001-05-01), Dortu et al.
patent: 6252443 (2001-06-01), Dortu et al.
patent: 6388485 (2002-05-01), Kim

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