Method for generating fill and cheese structures

Details Method for generating fill and cheese structures Method for generating fill and cheese structures

2006-08-16

2008-11-25

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07458053

ABSTRACT:
A multi-pass method for designing at least a portion of a circuit layout on a substrate is provided which includes receiving or generating a first level frame including an electrical component; generating a fill pattern on the first level frame outside of a forbidden area of said first level frame; generating a next level frame, the next level frame including the first level frame and a next level fill area outside of the first level frame; and adding a conductor to the next level frame. The conductor is connected to the electrical component, a first portion of the conductor is in the first level frame and a second portion of the conductor is in the next level fill area. The method includes generating a next fill pattern on the next level fill area outside of a forbidden area of said next level fill area, modifying the first level forbidden area to extend at least over the electrical component and the first portion of the conductor, and removing any of the plurality of structures in the fill pattern that are within the modified first level forbidden area.

REFERENCES:
patent: 5636133 (1997-06-01), Chesebro et al.
patent: 5923563 (1999-07-01), Lavin et al.
patent: 6223331 (2001-04-01), Juengling
patent: 6434732 (2002-08-01), Juengling
patent: 6499135 (2002-12-01), Li et al.
patent: 6507930 (2003-01-01), Bass, Jr. et al.
patent: 6637013 (2003-10-01), Li
patent: 7231624 (2007-06-01), Vuong et al.
patent: 7269807 (2007-09-01), Shimada et al.
patent: 7328419 (2008-02-01), Vuong et al.
patent: 2002/0185664 (2002-12-01), Dixit et al.
patent: 2004/0255259 (2004-12-01), Tan et al.
Laura Peters, “DFM: Worlds Collide, Then Cooperate”, Jun. 1, 2005, Semiconductor International Jun. 1, 2005, available at http://www.reed-electronics.com/semiconductor/index.asp?layout=articlePrint&articleID=CA604505, 11 pages.
Yu Chen et al., “Compressible Area Fill Synthesis”, IEEE Transactions on Computer—Aided Design of Integrated Circuits And Systems, vol. 24, No. 8, Aug. 2005, pp. 1169-1187.
MentorGraphics, “Calibre DESIGNrev Datasheet”, available at http://www.mentor.com/products/ic—nanometer—design/cl—floorplan/calibre—designrev/upload/DESIGNrev.pdf, 2 pages.
Mentor Graphics, “Calibre LFD Datasheet”, available at http://www.mentor.com/products/ic—nanometer—design/b1—phy—design/calibre—1fd/upload/calibre—1fd.pdf, 3 pages.
Jacob Bakker, “Using Calibre in a Design for Manufacturability Environment”, paper presented at the 2001 IC Design Technical Forum, available at http://www.mentor.com/dsm, 5 pages.

Affiliated with

Also associated with

Rating

Method for generating fill and cheese structures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for generating fill and cheese structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for generating fill and cheese structures will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4031484