Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
1999-12-06
2001-11-13
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S027000
Reexamination Certificate
active
06316964
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for generating differential tri-states and a differential tri-state circuit being able to output three states including a first signal state, a second signal state and a high impedance state.
2. Description of the Related Art
To transmit a logic signal between integrated circuits by using two signals each having a small-amplitude to be transmitted through transmission paths such as two bus lines in communication systems, computers and the like, two methods, one being a single-phase transmission system and the other being a differential-phase transmission system, are available. In the single-phase transmission system, one small-amplitude signal for transmission use is transmitted through two bus lines. In the differential-phase transmission system, two signals are used, i.e., a small-amplitude signal, which is equivalent to the signal used in the single-phase transmission system, is transmitted through one line of the two bus lines and a small-amplitude signal being in reverse phase is simultaneously transmitted through the other line of the two bus lines.
Operations of the differential-phase transmission system are described below. In the differential-phase transmission system, to transmit a logic signal between integrated circuits by using two signals to be transmitted through two bus lines, an output circuit to send out a logic signal to these transmission paths is used. If one signal being transmitted through one of two transmission paths is at a high level, it is defined as a logical 1 and the other signal being transmitted through the other of the two transmission paths is at a low level, it is defined as a logical 0 (zero). That is, a logic signal (hereinafter referred to as a “transmission signal”) to be transmitted by the output circuit is composed of two signals to be transmitted through the two transmission paths. Moreover, when the output circuit is outputting the logical 1 or 0, it is hereinafter defined that “the output circuit is outputting the 1 state or 0 state”.
Conventionally, an amplitude of a voltage between a high level signal and a low level signal is near to that of a supply power voltage applied to integrated circuits in most cases. However, in recent years, the amplitude of the voltage applied between the high level signal and the low level signal is made small for transmission purpose. For example, in an output circuit using conventional CMOS interface specifications, an amplitude of the transmission signal is approximately equal to a supply power voltage, i.e., about 5 volts or about 3 volts, in general. On the other hand, in an output circuit using LVDS (Low Voltage Differential Signaling) interface specifications, an amplitude of the transmission signal is as extremely small as about 0.3 volts.
The reasons for making an amplitude of the transmission signal so small are that such a small-amplitude signal is greatly effective in high speed transmission, low power consumption and reduction of noise occurring during the signal transmission. Therefore, in an integrated circuit seeking high speed transmission and low power consumption, it is necessary to use a small-amplitude interfacing output circuit to send out a signal having a small-amplitude. In such a small-amplitude interfacing output circuit, a transmission signal having a small-amplitude voltage being less than the power supply voltage is employed to achieve the high speed transmission, low power consumption and reduction of noise. Known small-amplitude interfacing output circuits include, in addition to the LVDS circuit described above, GRL (Gunng Transceiver Logic), CTT (Center Tapped Termination), PECL (Psuedo Emirter Coupled Logic) circuits.
For example, in the case of the PECL circuit, though its power supply voltage is about 3 volts or 5 volts, an amplitude of a transmission signal to be employed is about 0.6 volts. As a means to transfer such small-amplitude signals, a terminating voltage source and terminating resistors are used.
A conventional small-amplitude interfacing output circuit having the configurations described above is shown in FIG.
12
. The small-amplitude interfacing output circuit contains a differential tri-state circuit
1
T. Though the terminating voltage source VS and terminating resistors RT
1
and Rt
2
to be used in the small-amplitude interfacing output circuit are connected to transfer lines L
1
and L
2
as shown in
FIG. 12
, they may be mounted within the differential tri-state circuit as shown in FIG.
9
. However, even if the terminating voltage source VS is mounted within the differential tri-state circuit, the terminating voltage is supplied through the transfer lines L
1
and L
2
to the outside.
The differential tri-state circuit
1
T is connected to, for example, a CMOS internal circuit
52
of a first integrated circuit
50
. The transfer lines L
1
and L
2
are connected to an input circuit
1
R of a second integrated circuit
54
to receive a transmission signal. The input circuit
1
R is connected to a CMOS internal circuit
56
.
As shown in
FIGS. 9 and 10
, the differential tri-state circuit
1
T is comprised of a current source
2
, a current source
4
, a switching circuit
1
S in which a drain of a p-channel MOS FET P
3
is connected to a drain of an n-channel MOS FET N
3
, a source of the p-channel MOS FET P
3
is connected to a flow-out terminal NodeP of the current source
2
, a source of an n-channel MOS FET N
3
is connected to an inflow terminal NodeN of the current source
4
, a drain of a p-channel MOS FET P
4
is connected to a drain of an n-channel MOS FET N
4
, a source of the p-channel MOS FET P
4
is connected to the flow-out NodeP of the current source
2
and a source of an n-channel MOS FET N
4
is connected to the inflow terminal NodeN of the current source
4
and a switching voltage generating circuit
10
in which an output terminal
21
used to output a switching voltage signal APA is connected to a gate of the p-channel MOS FET P
3
, an output terminal
29
used to output a switching voltage signal APB is connected to a gate of the p-channel MOS FET P
4
, an output terminal
25
to output a switching voltage signal ANA is connected to a gate of the n-channel MOS FET N
3
and an output terminal
31
to output a switching voltage signal ANB is connected to a gate of the n-channel MOS FET N
4
.
The p-channel MOS FETs P
3
and P
4
are composed of MOS FETs which have been produced under the same manufacturing conditions and have the same configurations. The n-channel MOS FETs N
3
and N
4
are composed of MOS FETs which have been produced under the same manufacturing conditions and have the same configurations.
The current source
2
is comprised of a p-channel MOS FET P
1
a source of which is connected to a voltage source VDD having, for example, a predetermined voltage being 3 volts and a drain of which is connected to a current flow-out terminal NodeP, a p-channel MOS FET P
2
a source of which is connected to the voltage source VDD, a gate of which is connected to a gate of the p-channel MOS FET P
1
and the gate and a drain of which are connected to each other, and a current source
6
connected between the drain of the p-channel MOS FET P
2
and a ground potential point.
The current source
4
is comprised of an n-channel MOS FET N
1
a source of which is connected to a predetermined voltage value point, for example, a ground potential point and a drain of which is connected to a current flow-out terminal NodeN
1
, an n-channel MOS FET N
2
a source of which is connected to a ground potential point, a gate of which is connected to a gate of the n-channel MOS FET N
1
and the gate and a drain of which are connected to each other and a current source
8
connected between a drain of the n-channel MOS FET N
2
and a voltage source VDD.
A switching voltage supply circuit
10
has a switching voltage generating portion
10
S which is comprised of inverters
16
and
18
connected in series to an input terminal
12
, a NAND circu
Cho James H
McGuireWoods LLP
NEC Corporation
Tokar Michael
LandOfFree
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