Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-01-18
2005-01-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06845494
ABSTRACT:
What is disclosed is a method for budgeting timing in a hierarchically decomposed integrated circuit design, which includes: 1) optimizing at least one path through block pins, the optimization resulting in assigned gains for all the cells along said at least one path; 2) performing timing analysis on the at least one path, the timing analysis using the assigned gains in order to generate arrival times for signals at said block pins; and 3) deriving a tinting budget by examining said generated arrival times at said block pins.
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Burks Timothy M.
Riepe Michael A.
Savoj Hamid
Swanson Robert M.
Vahtra Karen E.
Lin Sun James
Magma Design Automation Inc.
Pillsbury & Winthrop LLP
Siek Vuthe
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