Method for generating and transferring redundancy bits between l

Details Method for generating and transferring redundancy bits between l Method for generating and transferring redundancy bits between l

1997-11-12

2000-03-28

Peikari, B. James

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

714 6, 714710, 711133, 712300, G06F 1108

Patent

active

060444371

ABSTRACT:
A method and apparatus are provided for reducing the number of cache line data transfers among components of a computer system, thus reducing the amount of traffic on a bus and increasing overall system performance. A sideband communication line is provided to transfer information from a source cache agent pertaining to redundant data strings occurring in a cache line to a destination cache agent. If redundant data strings occur in a cache line, the transfer of one or more portions of a cache line from the source to the destination can be canceled. Redundancy logic is provided to detect occurrences of redundant data strings located in a given cache line, generate and transfer redundancy bits when predetermined redundant data strings occur and decode redundancy bits at a destination cache agent to determine whether redundant data strings occur in subsequent cache lines to be transferred. The components benefiting from this invention can include a processor with its own on-chip L1 cache, a L2 or L3, an I/O controller or any other component that can perform cache functions. Alternative embodiments are provided of redundancy logic operating in parallel with data and instruction busses as well as redundancy logic operations occurring serially with the data and instruction busses.

REFERENCES:
patent: 5561779 (1996-10-01), Jackson et al.
patent: 5634109 (1997-05-01), Chen et al.
patent: 5829027 (1998-10-01), Goodrum
patent: 5883640 (1999-03-01), Hsieh et al.

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