Method for generating an FPGA two turn routing structure with la

Details Method for generating an FPGA two turn routing structure with la Method for generating an FPGA two turn routing structure with la

1998-07-17

2000-12-19

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, 716 17, H03K 19177

Patent

active

061631671

ABSTRACT:
A method for generating a two-turn programmable routing structure is provided for a programmable logic device that provides a high degree of routing flexibility, with lane-changing capability, while requiring a relatively small diffusion surface area. One routing structure generated according to the method of the invention provides lane-changing capability for every interconnect line in the structure and a fast path for each interconnect line running straight through the structure. The routing structure preferably comprises a unitary elongated diffusion area separated by voltage-controlled transistor gates into serially arrayed adjacent diffusion regions. The sequential diffusion regions are connected to interconnect lines having assigned directions, and can be grouped into sets of N directions, where N is a multiple of eight. The directions associated with the set of diffusion regions follow specified rules that impart the diffusion-sharing, lane-changing, and fast-path capabilities of the routing structure of the invention.

REFERENCES:
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patent: 4484292 (1984-11-01), Hong et al.
patent: 4777606 (1988-10-01), Fournier
patent: 5089973 (1992-02-01), Furtek
patent: 5504439 (1996-04-01), Tavana
patent: 5657242 (1997-08-01), Sekiyama et al.
patent: 5682107 (1997-10-01), Tavana et al.

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