Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-09-18
2009-08-04
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07571422
ABSTRACT:
The invention is a method for generating a design rule map having a spatially varying overlay error budget. Additionally, the spatially varying overlay error budget can be employed to determine if wafers are fabricated in compliance with specifications. In one approach a design data file that contains fabrication process information and reticle information is processed using design rules to obtain a design map with a spatially varying overlay error budget that defines a localized tolerance to overlay errors for different spatial locations on the design map. This spatially varying overlay error budget can be used to disposition wafers. For example, overlay information obtained from measured metrology targets on a fabricated wafer are compared with the spatially varying overlay error budget to determine if the wafer overlay satisfies the required specification.
REFERENCES:
patent: 2004/0233439 (2004-11-01), Mieher et al.
International Search Report in corresponding PCT application PCT/US07/79053, mailed Jul. 16, 2008.
Written Opinion in corresponding PCT application PCT/US07/79053, mailed Jul. 16, 2008.
Adel Michael
Chang Ellis
Do Thuan
KLA-Tencor Technologies Corporation
Suiter Swantz pc llo
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