Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-09-07
2001-07-10
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S236000, C327S269000, C327S270000
Reexamination Certificate
active
06259651
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the operation of a dynamic random access memory (DRAM) array. More specifically, the present invention relates to a method and structure for using a synchronous clock signal to control the internal operations of a DRAM array.
2. Description of the Prior Art
U.S. Pat. Nos. 5,708,624 and 5,615,169 issued to the same inventor and commonly owned as this Application and incorporated herein by reference in their entireties, are directed to controlling internal operations of a DRAM array. DRAM (Dynamic Random Access Memory) is well known, for instance in computer systems, for storage of data. U.S. Pat. No. 5,708,624 discloses method and structure for controlling the timing of an access to a DRAM array, for instance on an integrated circuit chip, in response to a row access signal and rising/falling edges of a clock signal. Row address decoding and the deactivation of equalization circuits are initiated when the row access signal is received and a first transition of the clock signal is detected. The row address decoding and the deactivation of the equalization circuits are completed before a second transition of the clock signal occurs.
A second transition is then used to initiate the turning on of the sense amplifiers of the DRAM array. The sense amplifiers are turned on before a third transition of the clock signal. The third transition of the clock signal is then used to initiate the column address decoding operation of the DRAM array. In an alternative embodiment, the column address decoding is initiated when a column access signal is asserted and the clock signal undergoes the third transition. The first, second and third transitions can be consecutive or non-consecutive edges of the clock signal. A problem with this prior art is that the DRAM array operations take more than one clock cycle. This is not compatible with a DRAM array that is intended for instance to be compatible with SRAM.
SUMMARY
Therefore in accordance with this invention a system clock signal is used to initiate the activation and deactivation of elements of a DRAM array, thereby eliminating timing uncertainties introduced by the delay elements of prior art DRAM accessing schemes and allowing all the DRAM array operations to be completed in one clock cycle.
Therefore the present address sequencing method involves receiving a system clock signal and an access signal which is asserted to initiate an access of the DRAM memory array. These two signals are received by a memory sequencer which generates the appropriate control signals including the row and column address signals for controlling operations of the memory array. This memory sequencer includes, in one embodiment, a phase locked loop (or alternatively a delay line clock phase generator) which outputs in one embodiment four timing signals per clock cycle. These timing signals bear a fixed phase relationship to the clock signal irrespective of the clock signal frequency. (In contrast, other prior approaches use delay lines to generate timing signals which have no phase relationship with the clock.)
These four timing signals are each applied to the clock and reset terminals of D-type registers where four such D-type registers are chained together. The first D-type register has its data terminal driven by the memory access signal. Therefore the four registers output the four needed control signals which are e.g. a row address signal, a column address signal, a turn on of sense amplifier signal, and a turn off of the column switches, sense amplifiers, word line and equalization of the bit line. The phase locked loop (or alternative clock phase generator) is such that the four control signals maintain fixed phase relationships inside each clock period. The embodiment with the clock phase generator uses a delay line arrangement with multiple delay lines which are chained together to provide the desired timing signals.
The present method allows an SRAM compatible device to be built from such DRAM or 1-Transistor cells. By utilizing the unused external access time for performing the infrequent memory refresh, this approach does not impose a penalty on the peak bandwidth requirement of the memory array.
REFERENCES:
patent: 5615169 (1997-03-01), Leung
patent: 5708624 (1998-01-01), Leung
patent: 5778237 (1998-07-01), Yamamoto et al.
patent: 5808961 (1998-09-01), Sawada
patent: 5829026 (1998-10-01), Leung et al.
patent: 6020773 (2000-02-01), Kan et al.
patent: 6052011 (2000-04-01), Dasgupta
Dinh Son T.
Holmbeck Signe M.
Klivans Norman R.
MoSys, Inc.
Skjerven Morrill & MacPherson LLP
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