Method for fully planarized conductive line for a stack gate

Details Method for fully planarized conductive line for a stack gate Method for fully planarized conductive line for a stack gate

1997-12-17

2000-02-22

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438622, 438626, 438692, 438257, 438649, H01L 214763

Patent

active

060279982

ABSTRACT:
A method for substantially reducing conductive line cracking on an integrated circuit, comprising the steps of: obtaining a semiconductor structure with a first surface and with an insulating region adjacent to and rising above the first surface; forming a layer of a first conductive material above the first surface of the semiconductor structure and above the adjacent first insulating region; forming an opening through the layer of first conductive material down to the first insulating region; forming an insulation layer over the layer of first conductive material; forming a layer of a second conductive material above the insulation layer; polishing the layer of second conductive material; and forming a third conductive layer above the layer of second conductive material.

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