Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-29
2001-10-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S411000, C438S421000, C438S623000, C438S633000, C438S686000, C438S687000
Reexamination Certificate
active
06306754
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the fabrication of semiconductor devices and more particularly to the use of air gaps as a low-dielectric constant material between metal lines and features.
BACKGROUND OF THE INVENTION
The trend in the semiconductor industry toward smaller devices and more densely packed designs on microelectronic substrates continues to create new challenges. One of the more recent obstacles to improvements in device performance is the need to reduce the dielectric constant of the materials between closely packed metal lines in a metallization layer. Metal lines in close proximity within a metallization layer have a parasitic capacitance which can lead to ‘cross-talk’ between lines as well as slower device performance.
One method for reducing the parasitic capacitance between nearby metal lines is to reduce the effective dielectric constant between the metal lines. Ideally, the dielectric constant between the metal lines could be reduced to 1, the dielectric constant of vacuum and the theoretical minimum. Traditionally the space between metal lines has been filled with SiO
2
, which typically exhibits dielectric constants between 3.5-4.0. All of the technological problems associated with working with SiO
2
are well-characterized, so SiO
2
provides a convenient material as the interlayer dielectric. SiO
2
also has the necessary structural integrity to support the multiple levels present in modern multi-level metallization stacks used to connect densely packed devices.
One potential solution to the parasitic capacitance problem is the use of porous SiO
2
instead of SiO
2
as the dielectric. Porous SiO
2
structures are partially composed of air due to the presence of a network of pores running throughout the structure. Depending on the percentage of the total volume occupied by the pores, porous SiO
2
layers can have dielectric constants approaching 2.
Due to difficulties in forming porous SiO
2
layers, however, it is difficult to consistently reproduce the lowest dielectric constant values. Porous dielectric layers are typically deposited by spin-on techniques. The initial deposition material is an alcohol-based solution with solvated ‘monomer’ units, such as silicon alkoxides, which will eventually form the porous dielectric. After deposition of the alcohol solution, a reaction is induced between the monomer units, eventually resulting in the formation of the porous dielectric. The pore size and total pore density can be controlled by controlling the reaction conditions during formation of the porous layer. At this point, however, the porous dielectric is still saturated with the alcohol solvent used for the initial deposition. This solvent must be carefully extracted to avoid disruption of the porous dielectric. Due to surface tension effects, simple evaporation of the solvent by heating will often result in degradation of the porous dielectric.
Many techniques for extracting the solvent involve replacing the alcohol with a lower surface tension solvent. Other techniques involve increasing the temperature and pressure on the porous dielectric to beyond the critical point of the alcohol. While removing the supercritical alcohol leads to much less damage to the porous dielectric layer, the pressure and temperature conditions required to convert the alcohol into a supercritical fluid are quite severe. An interesting combination of the above techniques has been to use supercritical CO
2
. CO
2
becomes a supercritical fluid under much less severe conditions than most alcohols, and supercritical CO
2
is a suitable solvent for most alcohols.
Air is potentially a desirable dielectric for use between metal lines. The dielectric constant of air is very close to one, providing nearly the minimum possible value. Maintaining air gaps between nearby metal lines in a multi-level metallization stack, however, poses severe problems from a processing standpoint. Generally, creation of metal levels involves a number of steps, including depositions of blanket layers of metal or dielectric, etching processes to transfer patterns, and planarization and etchback processes to achieve layers of specified thickness and uniformity. Obviously, any gaps between metal lines which are exposed during deposition of a blanket layer will be filled in by the blanket layer.
U.S. Pat. No. 5,461,003 discloses a method for creating air gaps between metal leads in metallization layers. In this invention, after metal leads are formed on a substrate, the space between the leads is filled by depositing a polymer solid. After the polymer solid is etched back to below the tops of the metal leads, a porous dielectric is deposited on the substrate. The polymer solid is then removed through the porous dielectric by one of several methods, including dissolution with a solvent such as acetone, chemical ashing with oxygen, or volatilization with heat.
The above techniques are only partially effective at creating the desired air gap structures. Methods of removing the polymer solid by use of a solvent or solvent vapor suffer from the extremely low diffusivity of the solvent through the pores of the porous dielectric. As a result, the extraction efficiency of the polymer solid is low, leading to incomplete removal of the polymer solid and/or poor throughput. Methods involving chemical ashing with O
2
are not compatible with all types of metal lines and features which might be present in a metallization stack. O
2
will attack Cu, resulting in increased resistance in metal lines. Barrier layers may also be attacked, including layers composed of TiN, TiSi
2
, and WN. As a result, chemical ashing of the polymer solid to remove the polymer as CO or CO
2
can often lead to increased resistance in metal lines and features.
Due to the difficulties encountered in the prior art, a need remains for an effective method of creating air gaps between metal lines in multi-level metallization stacks in microelectronic devices.
SUMMARY OF THE INVENTION
The present invention provides a method for creating multi-level metallization structures with air as the dielectric material between adjacent metal lines. The air gaps between the metal lines are created while leaving behind a minimum amount of residue in the air gap and with a minimum of damage to the metal lines.
After creating metal lines or features on a substrate, a blanket layer of a temporary structural solid, such as a photoresist, is deposited on the substrate. After deposition, the temporary structural solid is etched back so that at least the tops of the metal lines are exposed. A blanket layer of porous dielectric is then formed on the substrate over the metal features and the temporary structural solid. The substrate is then treated with a supercritical fluid, such as supercritical CO
2
. The supercritical fluid diffuses through the pores of the porous dielectric and dissolves the temporary structural solid. The dissolved temporary structural solid is transported out through the pores, leaving behind a minimum of residue between the metal lines with a minimum of damage to the metal lines.
REFERENCES:
patent: 4944837 (1990-07-01), Nishikawa et al.
patent: 5103288 (1992-04-01), Sakamoto et al.
patent: 5185296 (1993-02-01), Morita et al.
patent: 5409683 (1995-04-01), Tillotson et al.
patent: 5461003 (1995-10-01), Havemann et al.
patent: 5668398 (1997-09-01), Havemann et al.
patent: 5747880 (1998-05-01), Havemann et al.
patent: 5750415 (1998-05-01), Gnade et al.
patent: 5837630 (1998-11-01), Owens et al.
patent: 5879744 (1999-03-01), Cao et al.
patent: 5880026 (1999-03-01), Xing et al.
patent: 6063714 (2000-05-01), Smith et al.
List R.S., et al. Integration of Ultra-Low-K Xerogel Gapfill Dielectric for High Performance Sub-0.18 um Interconnects—pp. 77-78, 1997, Symposium on VLSI Technology Digest of Technical Papers.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Nguyen Ha Tran
Niebling John F.
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