Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-12-27
2001-08-07
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S696000
Reexamination Certificate
active
06271113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates a semiconductor device, and more particularly, to a method for forming a wiring in a semiconductor device, which allows to form a micron pattern below a critical resolution of an exposure.
2. Background of the Related Art
Even though a line width decreases the more as a device packing density of semiconductor devices becomes the higher, there has been a limitation in formation of a micron pattern only by an exposure due to the critical resolution in the photolithography.
A related art method for forming a wiring in a semiconductor device will be explained with reference to the attached drawings.
FIG. 1
illustrates a plan view of a related art wiring in a semiconductor device,
FIGS. 2
a
and
2
b
illustrate sections showing structures across lines I-I′ and II-II′ in
FIG. 1
without a cap layer respectively, and
FIGS. 3
a
and
3
b
illustrate sections showing structures across lines I-I′ and II-II′ in
FIG. 1
with a cap layer, respectively.
Referring to
FIG. 1
, the semiconductor device is provided with a cell array region, and a pad and peri region. As can be known from
FIG. 1
, though the pad and peri region has a comparatively large line width, the cell array region has a relatively small line width.
The related art method for forming a wiring in a semiconductor device will be explained.
Referring to
FIGS. 2
a
and
2
b
, a conduction layer
2
and a photoresist film
3
are deposited on a substrate
1
in succession for use as a wiring layer. And, the photoresist film
3
is subjected to patterning by exposure and development to form a wiring pattern mask. The wiring pattern mask is used in removing the conduction layer, selectively. Then, the photoresist film
3
is removed to form wiring in the cell array region and the pad and peri region, respectively.
Referring to in
FIGS. 3
a
and
3
b
, if a cap layer is provided on the wiring layer, the conduction layer
2
for use as the wiring layer, a cap layer
4
and the photoresist film
3
are deposited on the substrate
1
in succession. And, the photoresist film
3
is subjected to patterning by exposure and development, to form a wiring pattern mask. The wiring pattern mask is used in removing the cap layer
4
and the conduction layer
2
selectively. Then, the photoresist film
3
is removed, to form wiring on the cell array region and the pad and peri region, respectively.
And, though not shown, sidewalls may be used for forming a micron pattern. However, this method forms unnecessary pattern because the sidewalls are formed in four sides.
Thus, the related art method for forming a wiring in a semiconductor device has the following problems.
First, if the wiring is formed by exposure, a micron pattern below the critical resolution of the exposure can not be formed.
Second, even if a micron pattern beyond the micron pattern formation limit of the present exposure is formed by applying the sidewall method, the formation of the sidewalls all around a sacrificial pattern causes formation of sidewalls even at unnecessary portions, that in turn causes to form patterns even at unnecessary portions.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for forming a wiring in a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for forming a wiring in a semiconductor device, in which sidewalls are formed at desired portions only for forming a micron pattern below a critical resolution of exposure.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for forming a wiring in a semiconductor device having a cell array region and a peripheral region, includes the steps of (1) forming a conduction layer and a sacrificial wiring layer on a substrate in succession, (2) selectively removing the sacrificial wiring layer to form a virtual wiring line having a sloped end portion, (3) forming sidewall insulating films at sides of the virtual wiring line excluding the sloped end portion, (4) removing the virtual wiring line entirely, (5) forming a mask layer on regions of the pad and peri region pads and other wirings are to be formed thereon, and (6) using the mask layer and the sidewalls in removing the conduction layer selectively, to form a micron pattern.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4566941 (1986-01-01), Yoshida et al.
patent: 5227628 (1993-07-01), Okada et al.
patent: 6140219 (2000-10-01), Dennison
patent: 6150256 (2000-11-01), Furucava et al.
patent: 6153504 (2000-11-01), Shields et al.
Choi Sang Jun
Yang Wouns
Yoon Tak Hyun
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Smith Matthew
Yevsikov V.
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