Method for forming vias in multi-level integrated circuits, for

Details Method for forming vias in multi-level integrated circuits, for Method for forming vias in multi-level integrated circuits, for

1997-01-23

1999-01-19

Everhart, Caridad

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

438626, 438631, 438666, H01L 2941

Patent

active

058616730

ABSTRACT:
A process has been developed that allows reliable fabrication of vias, used for multi-level wiring purposes. The process features the use of a metallization structure, overlying a pillar structure in a specific area, resulting in a raised and extended metal surface, in areas of overlap. The raised and extended metal surface is used for subsequent via contact. Spin on glass processes are also employed to fill narrow spaces between metal structures.

REFERENCES:
patent: 4708770 (1987-11-01), Pasch
patent: 4874719 (1989-10-01), Kurosawa
patent: 4917759 (1990-04-01), Fisher et al.
patent: 5312512 (1994-05-01), Allman et al.
patent: 5346411 (1994-09-01), Pasch
patent: 5364818 (1994-11-01), Ouellet
patent: 5471091 (1995-11-01), Pasch et al.
patent: 5512514 (1996-04-01), Lee

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