Method for forming vias in a substrate

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S672000, C438S700000, C438S780000, C257SE21007, C257SE21170, C257SE21006, C257SE21058, C257SE21222, C257SE21229, C257SE21237

Reexamination Certificate

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07816265

ABSTRACT:
A method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.

REFERENCES:
patent: 5308443 (1994-05-01), Sugihara
patent: 5998292 (1999-12-01), Black et al.
patent: 6700175 (2004-03-01), Kodama et al.
patent: 6809421 (2004-10-01), Hayasaka et al.
patent: 7222420 (2007-05-01), Moriizumi
patent: 7276787 (2007-10-01), Edelstein et al.
patent: 2004/0259292 (2004-12-01), Beyne et al.
patent: 2006/0001174 (2006-01-01), Matsui
patent: 2007/0048896 (2007-03-01), Andry et al.

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