Method for forming vias and trenches in an insulation layer for

Details Method for forming vias and trenches in an insulation layer for Method for forming vias and trenches in an insulation layer for

1998-09-02

2000-08-01

Utech, Benjamin L.

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438702, 438753, H01L 21302

Patent

active

060966556

ABSTRACT:
In a dual-damascene processes for multi level interconnection a method for forming trenches and vias in the inter-insulation is accomplished without etching out the inter-insulation layer. A thick sacrificial layer is first deposited and reversed etched to form sacrificial pillars 64 forming the vias and sacrificial bridges 72 forming the trenches. The sacrificial layer can be any material (insulator, semiconductor, or metal), provided it can be easily patterned and selectively removed later over the inter insulator layer. Thereafter a low-k inter-insulation layer is deposited around the sacrificial pillars and bridges. It is these sacrificial pillars and bridges that are etched away leaving behind vias and trenches in the inter-insulation layer. An advantage of the invention is that it replaces a difficult RIE process of vias and trenches with a much easier RIE of sacrificial pillars and bridges. In the preferred embodiment, a silicon film, either amorphous or polycrystalline, is used as the sacrificial layer.

REFERENCES:
patent: 5652182 (1997-07-01), Cleeves
patent: 5723381 (1998-03-01), Grewal et al.
patent: 6033977 (1998-03-01), Gutsche et al.

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