Method for forming via hole and semiconductor structure formed t

Details Method for forming via hole and semiconductor structure formed t Method for forming via hole and semiconductor structure formed t

1998-07-31

2000-11-28

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257752, 257750, 257758, H01L 2348, H01L 2552, H01L 2940

Patent

active

061539368

ABSTRACT:
A method for manufacturing a semiconductor structure having a via hole is provided. The method includes steps of providing a base, forming a pad on the base, forming a device on the pad, forming a dielectric layer over the device and the base, executing a planarization process with etch back, and etching the dielectric layer to form the via hole. The manufactured semiconductor structure has a dielectric layer having therein the via hole, a device under the dielectrc layer, and a pad under the device for raising the device. The method and structure can prevent a residue due to planarization process from being remained between the dielectric layer and the device.

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patent: 5736791 (1998-04-01), Fujiki et al.

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