Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-03-20
2008-12-02
Nhu, David (Department: 2895)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S769000, C438S775000, C438S474000, C257SE21170, C257SE21257, C257SE21269, C257SE21274, C257SE21311, C257SE21227
Reexamination Certificate
active
07459390
ABSTRACT:
The present invention provides a method for manufacturing a semiconductor device having multiple gate dielectric thickness layers. The method, in one embodiment, includes forming a first layer of gate dielectric material over a semiconductor substrate in a first active region and a second active region of a semiconductor device, and patterning a masking layer to expose the first layer of gate dielectric material located in the first active region. The method further includes subjecting exposed portions of the first layer of gate dielectric material to a nitrogen containing plasma, thereby forming a second layer of gate dielectric material over the first layer of gate dielectric material located in the first active region, incorporating oxygen into the second layer of gate dielectric material located in the first active region, and removing the, patterned masking layer, thereby resulting in a first greater thickness gate dielectric in the first active region and a second lesser thickness gate dielectric in the second active region.
REFERENCES:
patent: 5989962 (1999-11-01), Holloway et al.
patent: 6110842 (2000-08-01), Okuno
patent: 6297103 (2001-10-01), Ahn et al.
patent: 6335262 (2002-01-01), Crowder et al.
patent: 6586339 (2003-07-01), Plat et al.
patent: 6730566 (2004-05-01), Niimi et al.
patent: 6756635 (2004-06-01), Yasuda et al.
patent: 7183596 (2007-02-01), Wu et al.
patent: 2005/0106894 (2005-05-01), Akoi et al.
patent: 2006/0043369 (2006-03-01), Varghese
patent: 2006/0046407 (2006-03-01), Juengling
patent: 2007/0218636 (2007-09-01), Niimi et al.
patent: 2007/0243683 (2007-10-01), Niimi et al.
Laaksonen Reima Tapani
Niimi Hiroaki
Brady III Wade J.
Nhu David
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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