Method for forming tungsten bit line and devices including...

Details Method for forming tungsten bit line and devices including... Method for forming tungsten bit line and devices including...

1999-11-18

2003-09-02

Cao, Phat X. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S621000, C438S629000, C438S643000, C438S659000, C438S675000

Reexamination Certificate

active

06613670

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a bit line in a semiconductor device, and more particularly, to a method for forming a tungsten bit line. The present invention also relates to devices that include these bit lines.
2. Background of the Related Art
In general, as a semiconductor device, such as a DRAM and the like, is packed highly, a bit line of doped polysilicon or a stack of tungsten silicide (WSi
x
)/polysilicon is used. However, when such a bit line is used, an operation speed drop occurs due to the high resistivity of the bit line. Further, when the bit line consists of doped polysilicon, the doping type of the polysilicon used for the bit line is changed according to the doping type of the silicon substrate which is in contact with the bit line. To prevent the doping type change of the doped polysilicon, contact with the silicon substrate is made through an additional metal, complicating the fabrication process and increasing the device size. Accordingly, to solve this problem, there has recently been research on using tungsten (resistivity of approx. 10-15 &mgr;&OHgr;cm), which has a resistivity significantly lower than tungsten silicide WSi
x
(resistivity of approx. 80-90 &mgr;&OHgr;cm). However, because a titanium layer, used as a contact layer to a tungsten bit line, reacts with the silicon substrate to form a titanium silicide TiSi
x
layer which is subsequently agglomerated during a high temperature heat treatment conducted in forming a capacitor, the tungsten bit line has the problems of high contact resistance or junction leakage.
In the case of a trench-capacitor-type-DRAM, where the capacitor is formed before the bit line, a heat treatment at a temperature over 600° C. is not required in fabrication processes performed after the bit line is formed. However, in the case of a DRAM, where the capacitor is formed after the bit line, because the heat treatment is carried out at a temperature over 600° C. in forming a capacitor, the heat treatment causes a reaction between the titanium layer Ti, used as a contact layer to the tungsten bit line, and the silicon in the silicon substrate to form a titanium silicide layer TiSi
x
. The TiSi
x
layer is subsequently agglomerated, resulting in a reduction of contact size, an increase of contact resistance, or a breakage of contact of the source/drain junction.
A related art method for forming a bit line on a stack of tungsten silicide/polysilicon or of tungsten after forming a field oxide, a well, a gate line, an n-type and p-type source/drain impurity regions, and an ILD (inter-layer dielectric) layer will be explained with reference to the attached drawings. FIGS.
1
A~
1
D illustrate the steps of a related art method for forming a bit line consisting of a stack of tungsten silicide/polysilicon.
Referring to
FIG. 1A
, a field oxide film (not shown), a gate insulating film
2
, a gate line
3
consisting of a stack of polysilicon and tungsten silicide, a cap gate insulating film
4
, sidewall insulating films
5
, and cell and peripheral source/drain impurity regions
6
and
7
, respectively, are formed on a silicon substrate
1
. Here, the cell source/drain impurity region
6
, in the cell region, is of n-type, and the peripheral source/drain impurity region
7
, in a peripheral region, is of p-type. Then, a first inter-layer insulating film
8
is formed on the substrate
1
and subjected to photo-etching to remove the first inter-layer insulating film
8
selectively over the cell source/drain impurity region
6
and to form a bit line contact hole to the cell source/drain impurity region
6
. Though not shown in the drawing, the photoresist used in the photo-etching is removed, and cleaning and washing for removing a natural oxide film is carried out.
As shown in
FIG. 1B
, polysilicon
9
is deposited over the entire surface so as to fill the bit line contact hole, and is etched back, leaving the deposited polysilicon in the contact hole. In some cases, polysilicon is deposited thereon, again. A tungsten silicide layer
10
and an oxide film
11
are deposited in succession on the polysilicon
9
. Optionally, the oxide film
11
, deposited for capping the tungsten silicide layer
10
, may not be deposited.
As shown in
FIG. 1C
, photo-etching is conducted to remove the oxide film
11
, the tungsten silicide layer
10
, and the polysilicon layer
9
selectively and to form a bit line
16
.
As shown in
FIG. 1D
, a second inter-layer insulating film
12
is deposited on the entire surface for electrical discontinuation of the bit line from other lines. The second inter-layer insulting film
12
over the peripheral source/drain impurity region
7
is selectively removed to form a contact hole. A metal contact layer and a TiN/Ti barrier layer
13
is formed on the entire surface, and a metal layer
14
and a cap insulting film
15
are formed in succession and subjected to photo-etching to pattern a signal line.
A second related art method, for forming a bit line of tungsten, will be explained. FIGS.
2
A~
2
E illustrate the steps of a related art method for forming a bit line of tungsten.
Referring to
FIG. 2A
, a field oxide film (not shown), a gate insulting film
2
, a gate line
3
consisting of a stack of polysilicon and tungsten silicide, a cap gate insulating film
4
, sidewall insulating films
5
, and cell and peripheral source/drain impurity regions
6
and
7
are formed on a silicon substrate
1
. The cell source/drain impurity region
6
is of n-type, and the peripheral source/drain impurity region
7
is of p-type. Doped polysilicon
18
is then deposited for use as a contact plug and selectively removed to leave it only on the cell source/drain impurity region
6
. Then, a first inter-layer insulating film
8
is formed on the entire surface for electrical discontinuation between tungsten bit lines and is then subjected to photo-etching to form contact holes over the doped polysilicon layer
18
and over the peripheral source/drain impurity region
7
.
As shown in
FIG. 2B
, a thin titanium layer
19
is formed on the entire surface for use as a contact layer to a tungsten bit line. A titanium nitride film
20
is formed on the titanium layer
19
for use as a diffusion barrier layer to the tungsten bit line and a heat treatment is conducted in an RTP (Rapid Thermal Process) device or in a furnace to cause a reaction between the titanium layer
19
and the silicon substrate
1
, forming a titanium silicide TiSi
x
layer (not shown in
FIG. 2B
, but shown in
FIG. 3
as reference numeral
22
). The heat treatment is conducted at 600~750° C. for 10~120 seconds if the RTP device is used and at 550~650° C. for 1~60 minutes if the furnace is used. Then, a tungsten layer
21
is deposited on the entire surface.
As shown in
FIG. 2C
, an etch back is carried out to pattern the tungsten layer
21
and to leave the tungsten layer
21
only in the contact hole. The etch back may be a dry etching or may use a CMP (Chemical Mechanical Polishing) device.
As shown in
FIG. 2D
, a barrier layer
24
and a tungsten layer
25
are deposited again and patterned to form the tungsten bit line.
As shown in
FIG. 2E
, a nitride film
26
is deposited on the entire surface, serving as a cap on the tungsten bit line, and an oxide film
27
is formed on the nitride film
26
. Though not shown, a capacitor is formed on the oxide film
27
at a temperature higher than 600° C.
The related art method for forming a bit line has the following problems: First, the bit line of doped polysilicon or a stack of tungsten silicide/polysilicon results in slow operation speed due to a high resistance of the doped polysilicon or tungsten silicide/polysilicon layer. Second, in the case of CMOS, the doping type of the doped polysilicon used for the bit line is changed according to the doping type of the region of the silicon substrate with which the bit line is in contact. Also, the metal plug formed for solving this problem complicates the fabrication process and result

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