Method for forming trench isolation regions

Details Method for forming trench isolation regions Method for forming trench isolation regions

2000-03-08

2002-05-14

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S424000

Reexamination Certificate

active

06387776

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
The present application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 99-40951 filed on Sep. 22, 1999, the entire contents of which are hereby incorporated by reference for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a method for forming a semiconductor device, more particularly, to a method for forming trench isolation regions in a semiconductor device, which electrically isolates the semiconductor device and increases the density at which the semiconductor devices can be formed.
2. Description of the Related Art
Device isolation techniques play an important role in the design and performance of highly integrated semiconductor circuits by electrically isolating regions and devices therein from adjacent devices and regions. As the design of theses highly integrated semiconductor circuits becomes smaller and more detailed, the isolation techniques have also developed to meet these demands. LOCal Oxidation of Silicon (LOCOS) and Shallow Trench Isolation (STI) techniques are commonly used for forming isolation regions in a semiconductor substrate.
The LOCOS technique has been widely used because it is relatively simple. However, the LOCOS technique has some limitations. In particular, when applied to highly integrated devices such as 256M DRAM devices, oxide thinning and punch-through parastics may become severe.
FIGS. 1
a
-
1
f
illustrate schematic cross-sectional views of intermediate structures illustrating a method of forming trench isolation regions according to the conventional art, i.e., STI technique. As shown in
FIG. 1
a
, a pad oxide pattern
12
and a silicon nitride pattern
14
are formed by patterning a pad oxide layer and a silicon nitride layer in order to expose a part of a semiconductor substrate as a trench isolation region.
Thereafter, as shown in
FIG. 1
b
, a trench
16
is formed by an etching using the silicon nitride pattern
14
as an etching mask with a depth of about 3,000 through 5,000 Å.
Thereafter, as shown in
FIG. 1
c
, a silicon nitride liner layer
18
is formed on the semiconductor substrate including the trench
16
by using a Chemical Vapor Deposition (CVD) apparatus (not shown).
Thereafter, as shown in
FIG. 1
d
, an insulation material layer
20
, as a High Temperature-Undoped Silicate Glass (HT-USG) material, is formed on the silicon nitride liner layer
18
in the trench
16
by simultaneously introducing ozone gas and Tetra Ethyl Ortho-Silicate (TEOS) chemical in the CVD apparatus
Thereafter, as shown in
FIG. 1
e
, a first insulation layer
22
is formed by etching the insulation layer
20
by well-known Chemical-Mechanical Polishing (CMP) in order to expose the surface of the silicon nitride layer
14
.
On the other hand, as shown in
FIG. 1
f
, a second insulation layer
24
is formed on the silicon nitride liner layer
18
of the finally fabricated semiconductor substrate
10
.
At an interface between trench isolation region including the silicon nitride liner layer
18
formed on the trench
16
and the second insulation layer
24
of HT-USG material, a part of the second insulation layer
24
is separated, resulting in damages. The encircled area labeled “A” in FIG. If is shown in detail in
FIG. 3
a
. As can be seen therein, a damaged part of the trench isolation region for isolating the field region and the active region is shown shaded. This damaged part will be explained relative to
FIG. 3
b
below in the discussion of the details of the present invention.
As described above, the damage of a resultant insulation layer is due to the stress arising from the differences between the coefficient of thermal expansion at the interface. The damage can also arise from using an HT-USG material having relatively low density from an ion implantation process. That is, from the beginning of the formation of the isolation region, the insulation layer does not uniformly grow on the silicon nitride liner layer, so that the insulation layer is separated at the interface of the silicon nitride liner layer and the insulation layer. Accordingly, an electrical characteristic of the device damaged like this deteriorates and a leakage current is produced at the damaged part. Accordingly, the device may be operating abnormally. Finally, the device may have a severe problem, reducing the reliability of the semiconductor device.
U.S. Pat. No. 5,882,982 discloses an etching process for forming a trench in the semiconductor substrate which includes introducing several types of additional gases under predetermined conditions. U.S. Pat. No. 5,885,883 discloses a technique for obtaining an insulation layer having a uniform density including filling the trench and forming a reinforcing oxide layer on the sidewall of the trench in order. However, neither of these patents disclose a technique capable of obtaining a trench isolation region having a uniform density by only controlling the conventional gases, i.e., without introducing other additional gases.
SUMMARY OF THE INVENTION
The present invention is therefore directed to method for forming trench isolation regions which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
An object of the present invention is to solve the problems produced in the STI technique as explained above and to provide an improved method for forming a trench isolation region in which a uniform gas distribution region on the trench (at the state that a silicon nitride liner layer is formed on the trench) is formed in order to grow an insulation layer having a uniform density. Thereby, the damage is prevented and the insulation layer formed on the silicon nitride liner layer is not separated at the interface.
These and other objects, features and advantages of the present invention are provided by a method of forming trench isolation regions which include forming a trench on a surface of a semiconductor device with a predetermined depth; forming a nitride liner layer on the surface of the semiconductor including the trench; forming a gas distribution region which is uniformly distributed on the nitride liner layer; and forming an insulation layer by filling the trench after said forming of the gas distribution region.
The gas distribution region is preferably formed by introducing an ozone gas. The gas distribution region is formed by introducing ozone gas of 5,000 sccm during about three seconds.
After forming the gas distribution region, the filling of the trench is preferably formed by simultaneously introducing ozone gas and TEOS(Tetra Ethyl Ortho-Silicate) chemical. Even more preferably, ozone gas of about 5,000 sccm and TEOS chemical of about 80 mg until 100 seconds from the start are simultaneously introduced.
After forming the gas distribution region the filling of the trench is achieved that according to simultaneously introducing ozone gas and the TEOS chemical, a surface reaction between the gas distribution region and the ozone gas and TEOS chemical is started at the interface and grown, so that a layer having a uniform density is formed.
Other objects and features of the present invention will become more apparent and the invention itself will best be understood by referring to the following description and embodiments taken in conjunction with the accompanying drawings.


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Vossen and Kern Thin Film Processing II Acedemic Press 1991 p. 323.*
S. Wolf Silicon Processing for the VSLI Era vol. 3 Lattice press 1995 p. 372.

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