Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2001-01-25
2002-05-07
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S663000
Reexamination Certificate
active
06383901
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for forming a shallow junction, more particularly, to the method for forming a ultra-shallow junction by using a arsenic plasma doping fashion. The present invention uses the arsenic plasma doping fashion to dope arsenic ions to the junction of the semiconductor and then passes through a post anneal process to reduce the region of the junction successfully. The junction will become a low resistance ultra-shallow junction.
2. Description of the Prior Art
In general, in a semiconductor device, a semiconductor element is formed by providing an impurity diffusion layer in a semiconductor substrate. The impurity diffusion layer is provided by forming, for example, an SiO.sub.2 film, on a surface of a semiconductor substrate by a thermal oxidation method, patterning the SiO.sub.2 film by photolithography technology, and carrying out a selective thermal-diffusion of impurities or an ion-implantation using the SiO.sub.2 film as a mask.
The thermal diffusion process, however, comprises an annealing step at a high temperature, and thus impurities are diffused not only in the depth direction but also in the width direction. Consequently, it is difficult to control the diffusion of the impurities only in the depth direction. Particularly, when for example, an impurity having a large diffusion coefficient, for example, boron (B), is diffused, the impurity diffusion in both the width and depth directions is large, and thus a shallow junction can not be easily formed.
In the ion implanting process, the annealing process required for activating impurities and recovering damage takes a long time, thereby causing a redistribution of the implanted ions and the occurrence of a channeling phenomenon due to a particular crystalline orientation. Consequently, it is also difficult to form a shallow junction by ion-implantation, as it is in the above-mentioned thermal diffusion process.
When the shallow junction is formed by using the traditional ion-implantation technology, the energy of the ion-implantation is ultra-low. The energy of the beam current of this ion-implantation is about lower than 1000 kilo-electric voltage (keV). The energy of this implanted beam current is over low and is a tenth of the last generation technology. This condition will affect the throughput seriously. Therefore, the traditional method can not be almost used in the modern process, which emphasizes the output ability of the unit space.
In the traditional ion-implantation technology, we also use the wafer tilt way to implant ions into the whole junction. But in the wafer tilt ion-implantation process, the implanted ions in the junctions, which are on the both side of the gate, are not the same. This condition will make the resistance values of the both junctions be non-uniform and will affect the quality of the productions. This condition will also decrease the throughput because of adding the wafer tilt process. Therefore, In accordance with the above statement, the traditional ion-implantation method is not suitable to produce the shallow junction. Especially the main objective of the present semiconductor process is to reduce the volume of the semiconductor element and to increase the density of the semiconductor elements in the semiconductor. When the volume of the element is reduced, the region of the junction must be following reduced to become the ultra-shallow junction. The functions of the element and the throughput of the factory must be also maintained. Therefore, the present invention is used for producing the ultra-shallow junction in the semiconductor, reducing the resistance value of the ultra-shallow junction, and not affecting the throughput of the process.
SUMMARY OF THE INVENTION
In accordance with the above-mentioned invention backgrounds, the traditional ion-implantation method can not form the needed ultra-shallow junction. The main objective of the present invention is to provide a method for forming the ultra-shallow junction by using a arsenic plasma doping fashion to control the region of the ultra-shallow Junction. The present invention will reduce the region of the ultra-shallow junction successfully and not affect the electricity of the ultra-shallow junction.
The second objective of this invention is to prevent the arsenic ions diffusing to the outside of the needed depth in the post anneal process by using the arsenic plasma doping fashion to form the ultra-shallow junction.
The third objective of this invention is to reduce the spending time of the post anneal process to increase the throughput of the process by using the arsenic plasma doping fashion to form the ultra-shallow junction.
The fourth objective of this invention is to make the resistance of the ultra-shallow junctions which are on the both sides of the gate be the same by using the arsenic plasma doping fashion to form the ultra-shallow junction.
It is a further objective of this invention is to reduce the resistance value of the ultra-shallow junction and increase the qualities of the formed ultra-shallow junction by using the arsenic plasma doping fashion to form the ultra-shallow junction.
In according to the foregoing objectives, The present invention provide a method for forming a ultra-shallow junction by using the arsenic plasma doping fashion and then passing through a post anneal process. The depth of the doped arsenic ions in the semiconductor are controlled following the needs of the process to make the region of the junction be reduced following the reduced volume of the semiconductor elements to become the ultra-shallow junction. The electricity of the ultra-shallow junction which is formed by using the present invention method is better and the resistance value of the ultra-shallow junctions which are on the both sides of the gate is more uniform. The method of the present invention even more can reduce the proceeding time of the producing the ultra-shallow junction process, raise the throughput, and increase the qualities of the ultra-shallow junction.
REFERENCES:
patent: 5270250 (1993-12-01), Murai et al.
patent: 5672541 (1997-09-01), Booske et al.
patent: 6165858 (2000-12-01), Gardner et al.
patent: 6258682 (2001-07-01), Tseng
Macronix International Co. Ltd.
Nelms David
Nhu David
LandOfFree
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