Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-10-08
2004-10-05
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S622000, C438S647000
Reexamination Certificate
active
06800550
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming conductive wires of a semiconductor device, more particularly, to a method for forming conductive wires of a semiconductor device by utilizing a notching phenomenon of polycrystalline silicon.
2. Description of the Related Art
Semiconductor fabrication techniques attempt to attain high integration and high performance. Copper wiring is commonly used in the fabrication of semiconductor devices.
However, copper wires are difficult to etch using conventional etching materials. Due to this characteristic of copper wires, a damascene process is typically used in which an interlayer dielectric film is etched to form a trench, a copper layer is deposited to fill the trench, and the copper layer is then planarized.
There are various known methods for forming copper wires using the damascene process. For example, in one known process a trench is formed for the copper wire, and a via/contact hole is magnetically aligned.
Unfortunately, known methods have problems with lithography overlays, especially in semiconductor devices utilizing a design rule 0.13 &mgr;m. Using a design rule of 0.13 &mgr;m or below often results in misalignment of via/contact holes of up to 0.01 &mgr;m. It is difficult to control misalignment under 0.03 &mgr;m, especially using a stepper. The limit for misalignment for thickness uniformity of disposed layers and status of the stepper in a semiconductor device fabrication process is often greater than 0.07 &mgr;m. Thus, conventional damascene processes must be performed with many restrictions. In addition, the stepper itself has limits on overlays, since misalignment of the hole and the trench often occurs.
FIG. 1
a
is a cross sectional view illustrating a conventional process for forming a via/contact hole after forming a trench. First, a lower structure is formed at an upper portion of a semiconductor substrate
11
. A first interlayer dielectric film
13
is formed on the whole surface of substrate
11
. A lower metal wire mask, which exposes portions of substrate
11
for the lower metal wire, is used as an etching mask for etching the first interlayer dielectric film
13
to form a trench. A metal layer for wiring the lower metal is then formed on the surface of dielectric file
13
and an exposed portion of substrate
11
. For example, a copper film may be used for the metal layer as a lower metal wire. The metal layer then undergoes a chemical mechanical polishing (“CMP”) process to form the lower metal wire
15
.
A diffusion barrier layer
17
is formed on the whole surface having a predetermined thickness. The diffusion barrier layer
17
is typically a Si
3
N
4
or SiC film. A second interlayer dielectric film
19
is then formed on top of the diffusion barrier layer
17
.
An upper metal wire mask, which exposes portions for the upper metal wire, is used as the etching mask for etching the second interlayer dielectric film
19
based on a designated thickness and form a trench
23
. A photoresist film pattern
21
is formed on the surface of the second interlayer dielectric film
19
to expose a location for the via/contact hole. However, because of misalignment, the photoresist film pattern
21
may be formed such that an upper portion of dielectric film
19
is exposed also.
FIG. 1
b
is a cross sectional view showing another conventional process of forming a via/contact hole after forming a trench. The same steps explained in FIG.
1
a
are repeated up to formation of the second interlayer dielectric film
19
. Then, a via/contact mask is used as an etching mask for etching the second interlayer dielectric film
19
and form a via/contact hole
25
. In addition, a photoresist film pattern
21
is formed on the second interlayer dielectric film
19
to expose portions for the upper metal wire. Occasionally, the lower metal wire
15
is not exposed, especially when the photoresist film pattern
21
is embedded into the via/contact hole
25
, and the diffusion barrier layer
17
is not properly removed.
FIGS. 2
a
through
2
c
show the problems with the conventional processes for forming conductive wires in semiconductor devices.
FIG. 2
a
shows the problems of using N
2
or NH
3
to remove the photoresist film pattern after the via/contact hole is formed. In particular,
FIG. 2
a
shows a poisoning phenomenon in which acidic H
+
is produced in the exposed region of the photoresist film. During the process of forming the photoresist film pattern for the trench mask, acidic H
+
may produced because of a reaction with an alkaline developing solution that is not properly dissolved or failed to become water (H
2
O). Instead, other remaining acidic ions in the via/contact hole, such as, NH
+
, NH
2
+
, or NH
3
+
, may cause the H
+
to remain undissolved and result in photoresist film in the shape of a mushroom.
FIG. 2
b
shows a dry etching process for forming the via/contact hole and the trench where no etching stop film is used in order to decrease parasitic permittivity between metal wires. As shown, the edge of the upper portion of the via/contact hole is collapsed due to a facet phenomenon, which is typically observed in the dry etching process.
FIG. 2
c
shows a trench etching process using the photoresist film pattern and embedding a part of the via/contact hole. As shown, a narrow gap between the via/contact hole and the trench causes etching byproducts that are produced by the trench etching process of the interlayer dielectric film to fill in the via/contact hole, and to attach to the photoresist film.
As explained above, traditional methods for forming conductive wires in semiconductor devices often cause misalignments during formation of the trench and the via/contact hole, and exhibits the problems shown in
FIGS. 2
a
through
2
c
, i.e., poisoning, facet, and attachment of etching byproducts, which cause lower process yields and may lower reliability of the semiconductor device.
Accordingly, it would be desirable to provide methods, which overcome these and other shortcomings of the related art.
SUMMARY OF THE INVENTION
In accordance with one embodiment consistent with the principles of the present invention, a method for forming a conductive wire of a semiconductor device, comprises: etching a lower portion of a side wall of a silicon layer pattern based on a difference of etching selectivities between a silicon layer and a lower film; and forming a T-shaped conductive wire based on the silicon layer pattern.
In accordance with another embodiment consistent with the principles of the present invention, a method for forming conductive wires of a semiconductor device comprises: forming a first interlayer insulating film on a semiconductor substrate having a lower metal wire to form a structure; forming a diffusion barrier layer over the structure; forming a sacrificial conductive layer on the diffusion barrier layer; forming a T-shaped sacrificial conductive layer pattern based on a photolithography process, an upper metal wire mask to etch a lower portion of a side wall of the sacrificial conductive layer, and a notching phenomenon; forming a planarized second interlayer insulating film based on exposing the sacrificial conductive layer, and a second interlayer dielectric film filling an under-cut of the T-shaped sacrificial conductive layer pattern; removing the sacrificial conductive layer pattern based on etching an exposed portion of the diffusion barrier layer to simultaneously form a via contact hole and a trench exposing the lower metal wiring; and forming an upper metal wire connected to the lower metal wire by filling the via contact hole and the trench.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 6528363 (2003-03-01), Ku et al.
patent: 1992-0013606 (1992-07-01), None
Notice of Preliminary Rejection from the Korean Intellect
Chen Jack
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hynix / Semiconductor Inc.
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